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522 Views
Registered: ‎01-21-2019

7 Series FPGAs GTX/GTH Transceivers “qplllock” signal

Hi all,

I am working on a XAUI example design simulation generated by VIVADO. The design is using 7 Series FPGAs GTX/GTH Transceivers.

I have a question about “qplllock” signal. The entire documentation explains the behavior of the signal once it goes from low to high during POR. My question is, once this signal goes high, under what conditions does it go from high to low?

I already tried to stop the “reflck” during the during the simulation but the signal remains high.

Regards

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5 Replies
Moderator
Moderator
478 Views
Registered: ‎05-02-2017

Re: 7 Series FPGAs GTX/GTH Transceivers “qplllock” signal

 

hi @javier.laboyjusino,

 

Thanks for contacting Xilinx Forms

 

Xilinx offer different type of transceivers , transceiver offerings cover the gamut of todayhigh speed protocols. The GTH and GTY transceivers provide the low jitter required for demanding optical interconnects and feature world class auto-adaptive equalization with PCS features required for difficult backplane operation.

for example :

  • UltraScale+ GTR (6.0 Gb/s): Easiest integration of common protocols to the Zynq Processor Subsystem
  • UltraScale+ GTH (16.3 Gb/s): Low power & high performance for the toughest backplanes
  • UltraScale+ GTY (32.75 Gb/s) Maximum NRZ performance for the fastest optical and backplane applications; 33G transceivers for chip-to-chip, chip-to-optics, and 28G backplanes
  • UltraScale GTH (16.3 Gb/s): Low power & high performance for the toughest backplanes
  • UltraScale GTY (30.5 Gb/s): High performance for optical and backplane applications; 30G transceivers for chip-to-chip, chip-to-optics, and 28G backplanes
  • UltraScale+ GTM (58 Gb/s): Maximum performance using PAM4 for 58G chip-to-chip, chip-to-optics, and backplane applications
  • 7 Series GTP (6.6 Gb/s): Power optimized transceiver for consumer and legacy serial standards
  • 7 Series GTX (12.5 Gb/s): Lowest jitter and strongest equalization in a mid-range transceiver
  • 7 Series GTH (13.1 Gb/s): Backplane and optical performance through world class jitter and equalization
  • 7 Series GTZ (28.05 Gb/s): Highest rate, lowest jitter 28G transceiver in a 28nm FPGA
  • Spartan-6 GTP (3.2 Gb/s): Power and cost optimized transceiver for cost-sensitive application.

 

   for more information please see the ug467 and high speed Serial IO made easy .

 

below are links

https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf.

https://studylib.net/doc/18454426/high-speed-serial-i-o-made-simple.

 

let me know your inputs

 

 

 

 

Regards
Chandra sekhar
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Xilinx Employee
Xilinx Employee
468 Views
Registered: ‎10-19-2011

Re: 7 Series FPGAs GTX/GTH Transceivers “qplllock” signal

Hi @javier.laboyjusino,

in  HW I would expect the qplllock signal to go low if the reference clock is missing. It depends now how the simulation model of the PLL is covering this.

Another question would be, at what point of the signal path are you looking at? Are you looking directly at the output of the transceiver primitive or some signal further out in the design, where it might be already captured by a FF? And with what clock is that FF clocked?
If you remove the refclk, the following stages in the qplllock signal path might not be clocked anymore and you will not see the signal going down.

If you give a PLL reset or power down and leave all clocks running, do you then see the signal going down?

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451 Views
Registered: ‎01-21-2019

Re: 7 Series FPGAs GTX/GTH Transceivers “qplllock” signal

Hi @eschidl

I have verified the signal that comes directly from the transceiver wrapper. The gt0_gpllock_out is not  being driven by external FF. I stopped the refclk but the gt0_gpllock_out remains high.

Thank you for your help

wave.PNG 

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Xilinx Employee
Xilinx Employee
437 Views
Registered: ‎10-19-2011

Re: 7 Series FPGAs GTX/GTH Transceivers “qplllock” signal

Hi @javier.laboyjusino,

did you try giving a reset? Is the lock going down then?

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425 Views
Registered: ‎01-21-2019

Re: 7 Series FPGAs GTX/GTH Transceivers “qplllock” signal

Hi @eschidl,

The Xilinx XAUI example design do a 700ns POR (Power-on Reset) and the "qplllock" signal is negate(Signal goes from high to low) during such time. Is there a way to negate the "qplllock" signal without doing a reset? 

Thank you for your help

wave.PNG

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