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bfung_2
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Registered: ‎07-02-2020

7-series GTX IBERT Example Design @ 0.625 Gbps

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Hello,

Running the IBERT example design at 1.25 Gbps on the GTX transceivers on the Zynq-7030 was a success (using a 125 MHz reference clock)

When I decrease the line rate to 0.625 Gbps, the IBERT indicates the transceiver PLLs cannot lock (all other settings are the same).

The GTX IBERT should support this line rate, but it seems the reference clock is incompatible with the 0.625 Gbps line rate? How should I resolve this?

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bfung_2
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Registered: ‎07-02-2020

The solution was to use the channel PLLs instead of the Quad PLL by unchecking the Quad PLL selection in the IBERT wizard.

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bfung_2
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566 Views
Registered: ‎07-02-2020

The solution was to use the channel PLLs instead of the Quad PLL by unchecking the Quad PLL selection in the IBERT wizard.

View solution in original post

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