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Explorer
Explorer
1,539 Views
Registered: ‎03-08-2018

A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

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Hi,

I'm trying to implement SRIO example 

But I've got the below error message, what am I supposed to do to resolve this problem?

 

[Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["D:/work/test_SRIO/test_SRIO3/srio_gen2_0_example/srio_gen2_0_example.srcs/constrs_1/imports/example_design/srio_gen2_0.xdc":55]

 

 

I set like this.

 

set_property PACKAGE_PIN AK5 [get_ports FPGA_SRIO0_TXN]
set_property PACKAGE_PIN AK6 [get_ports FPGA_SRIO0_TXP]
set_property PACKAGE_PIN AJ3 [get_ports FPGA_SRIO1_TXN]
set_property PACKAGE_PIN AJ4 [get_ports FPGA_SRIO1_TXP]
set_property PACKAGE_PIN AK1 [get_ports FPGA_SRIO2_TXN]
set_property PACKAGE_PIN AK2 [get_ports FPGA_SRIO2_TXP]

 

and FPGA is xc7k480tffg901-2.

 

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Accepted Solutions
Explorer
Explorer
1,988 Views
Registered: ‎03-08-2018

Re: A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

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When I change the xdc as the below

#-----------------------------------------------------------------------------
#
# File name:    srio_gen2_0.xdc
# Rev:          3.2
# Description:  This module constrains the example design
#
#-----------------------------------------------------------------------------
######################################
#         Core Time Specs            #
######################################

create_clock -period 8.000 -name sys_clkp -waveform {0.000 4.000} [get_ports sys_clkp]
set_case_analysis 0 [list [get_pins -hierarchical *mode_1x]]

set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *ack_sync_reg1}]
#set_multicycle_path -from [get_pins *cfg_raddr_reg* -hierarchical] -to [get_pins *cfg_reg*rdata_reg* -hierarchical] 3
#set_multicycle_path -from [get_pins *cfg_raddr_reg* -hierarchical] -to [get_pins *cfg_reg*rdata_reg* -hierarchical] 2 -hold

################################################################################
######################################################
##       GT and other Pin Locations                  #
## NOTE: These pins need to be updated for device:   #
## "xc7k480tffg901-2"#
## Below LOC's are given as dummy LOC's and          #
## need to be updated by the user                    #
######################################################

##  set_property LOC GTXE2_CHANNEL_X0Y8 [get_cells -hier -nocase -regexp {.*/gt_wrapper_i/gt0_gt_wrapper_i/gt.e2_i}]
##
##
set_property PACKAGE_PIN AD5 [get_ports sys_clkn]
set_property PACKAGE_PIN AD6 [get_ports sys_clkp]
 

set_property PACKAGE_PIN 	AC8	[get_ports 	sys_clkp2		]
set_property PACKAGE_PIN 	AC7	[get_ports 	sys_clkn2		]
set_property PACKAGE_PIN 	U8	[get_ports 	sys_clkp3		]
set_property PACKAGE_PIN 	U7	[get_ports 	sys_clkn3		]


set_property PACKAGE_PIN U17 [get_ports sys_rst]

set_property PACKAGE_PIN AK6 [get_ports FPGA_SRIO0_TXP]
set_property PACKAGE_PIN AK5 [get_ports FPGA_SRIO0_TXN]
set_property PACKAGE_PIN AJ12 [get_ports FPGA_SRIO1_TXP]
set_property PACKAGE_PIN AJ11 [get_ports FPGA_SRIO1_TXN]
set_property PACKAGE_PIN AF2 [get_ports FPGA_SRIO2_TXP]
set_property PACKAGE_PIN AF1 [get_ports FPGA_SRIO2_TXN]

#set_property PACKAGE_PIN AJ4 [get_ports FPGA_SRIO1_TXP]
#set_property PACKAGE_PIN AJ3 [get_ports FPGA_SRIO1_TXN]
#set_property PACKAGE_PIN AK2 [get_ports FPGA_SRIO2_TXP]
#set_property PACKAGE_PIN AK1 [get_ports FPGA_SRIO2_TXN]

set_property PACKAGE_PIN AH6 [get_ports FPGA_SRIO0_RXP]
set_property PACKAGE_PIN AH5 [get_ports FPGA_SRIO0_RXN]
set_property PACKAGE_PIN AH10 [get_ports FPGA_SRIO1_RXP]
set_property PACKAGE_PIN AH9 [get_ports FPGA_SRIO1_RXN]
set_property PACKAGE_PIN AB6 [get_ports FPGA_SRIO2_RXP]
set_property PACKAGE_PIN AB5 [get_ports FPGA_SRIO2_RXN]

#set_property PACKAGE_PIN AG4 [get_ports FPGA_SRIO1_RXP]
#set_property PACKAGE_PIN AG3 [get_ports FPGA_SRIO1_RXN]
#set_property PACKAGE_PIN AE4 [get_ports FPGA_SRIO2_RXP]
#set_property PACKAGE_PIN AE3 [get_ports FPGA_SRIO2_RXN]

set_property IOSTANDARD LVCMOS18 [get_ports sys_rst]
                                                                    
#set_property LOC GTXE2_CHANNEL_X0Y4  [get_cells srio_example_top_ip_srio_gen2_1_dsp_1/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt0_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y5  [get_cells srio_example_top_ip_srio_gen2_1_dsp_1/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt1_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells srio_example_top_ip_srio_gen2_1_dsp_2/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt0_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells srio_example_top_ip_srio_gen2_1_dsp_2/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt1_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y8  [get_cells srio_example_top_ip_srio_gen2_1_dsp_3/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt0_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y9  [get_cells srio_example_top_ip_srio_gen2_1_dsp_3/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt1_srio_gen2_1_i/gtxe2_i]


It's works. 

 

I have some question about this.

 

I see.. that should be assigned by generated SRIO logic setting. and I have to follow this rule. If I set 1 lane of 3 srio , then I have to use just *0 ports of 3 srio..

oh.. Thanks! now I understand what you are saying.

 

 

Now I have to resolve multi SRIO implementation in one Differential Clock source domain.

Actually I've the problem one more https://forums.xilinx.com/t5/7-Series-FPGAs/Can-I-make-3-differential-clock-from-1-differential-clock/m-p/846623#M26350

 

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7 Replies
Scholar dpaul24
Scholar
1,520 Views
Registered: ‎08-07-2014

Re: A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

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@love119,

 

You should look carefully into the "Master Constraints File Listing" of the FPGA you are using to find out your mistake.

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Xilinx Employee
Xilinx Employee
1,511 Views
Registered: ‎10-19-2011

Re: A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

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Hi @love119,

 

if you want to use the TX of X0Y4, X0Y5 and X0Y6 in bank 112 of the device the settings you show are correct for the ports to use.

But please check if you have additional constrains in your setup that are for the transceiver primitive location itself, like the X0Y4 I mentioned.

You should not have both of them together in your setup. Only one kind of constraint is allowed, either the ports or the primitive.

Even if they would match the same site, the SW will complain as they can contradict each other.

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Explorer
Explorer
1,485 Views
Registered: ‎03-08-2018

Re: A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

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If I want to use the RX of them, How do I set the device? I want to know more which bank and which cells are related with  RX.?

Actually, first time, I was just implemented with them like this.

#set_property PACKAGE_PIN AH6 [get_ports FPGA_SRIO0_RXP]
#set_property PACKAGE_PIN AH5 [get_ports FPGA_SRIO0_RXN]
#set_property PACKAGE_PIN AG4 [get_ports FPGA_SRIO1_RXP]
#set_property PACKAGE_PIN AG3 [get_ports FPGA_SRIO1_RXN]
#set_property PACKAGE_PIN AE4 [get_ports FPGA_SRIO2_RXP]
#set_property PACKAGE_PIN AE3 [get_ports FPGA_SRIO2_RXN]

 

But If I do  like this style, I can't avoid error message.

Should I have to have this style to use SERDES such as SRIO?

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Xilinx Employee
Xilinx Employee
1,444 Views
Registered: ‎10-19-2011

Re: A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

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Hi @love119,

 

please check out ug476, page 355. There you find bank112 with its primitives, which you use.

Channel X0Y4 for example includes the TX and RX.

So as said before, you either put one constraint to link the location of the primitive with the instantiation in your code or you set the location for the ports, for RX and TX.

But not both.

Please check in your project if you have the location for the primitive already given in the design at some place, maybe in an IP xdc, so that the ports constraints are not necessary anymore.

You could just comment out the port constraints that give you the error and implement the design, then check in the implemented design if the primitives and ports are placed correctly.

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Explorer
Explorer
1,426 Views
Registered: ‎03-08-2018

Re: A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

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Th


@eschidlwrote:

Hi @love119,

 

please check out ug476, page 355. There you find bank112 with its primitives, which you use.

Channel X0Y4 for example includes the TX and RX.

So as said before, you either put one constraint to link the location of the primitive with the instantiation in your code or you set the location for the ports, for RX and TX.

But not both.

Please check in your project if you have the location for the primitive already given in the design at some place, maybe in an IP xdc, so that the ports constraints are not necessary anymore.

You could just comment out the port constraints that give you the error and implement the design, then check in the implemented design if the primitives and ports are placed correctly.


Thanks, @eschidl

 

I've checked,

q181.JPG

 

and 

set_property PACKAGE_PIN AD5 [get_ports sys_clkn]
set_property PACKAGE_PIN AD6 [get_ports sys_clkp]
 

set_property PACKAGE_PIN 	AC8	[get_ports 	sys_clkp2		]
set_property PACKAGE_PIN 	AC7	[get_ports 	sys_clkn2		]
set_property PACKAGE_PIN 	U8	[get_ports 	sys_clkp3		]
set_property PACKAGE_PIN 	U7	[get_ports 	sys_clkn3		]


set_property PACKAGE_PIN U17 [get_ports sys_rst]

set_property PACKAGE_PIN AK6 [get_ports FPGA_SRIO0_TXP]
set_property PACKAGE_PIN AK5 [get_ports FPGA_SRIO0_TXN]
set_property PACKAGE_PIN AJ4 [get_ports FPGA_SRIO1_TXP]
set_property PACKAGE_PIN AJ3 [get_ports FPGA_SRIO1_TXN]
set_property PACKAGE_PIN AK2 [get_ports FPGA_SRIO2_TXP]
set_property PACKAGE_PIN AK1 [get_ports FPGA_SRIO2_TXN]

set_property PACKAGE_PIN AH6 [get_ports FPGA_SRIO0_RXP]
set_property PACKAGE_PIN AH5 [get_ports FPGA_SRIO0_RXN]
set_property PACKAGE_PIN AG4 [get_ports FPGA_SRIO1_RXP]
set_property PACKAGE_PIN AG3 [get_ports FPGA_SRIO1_RXN]
set_property PACKAGE_PIN AE4 [get_ports FPGA_SRIO2_RXP]
set_property PACKAGE_PIN AE3 [get_ports FPGA_SRIO2_RXN]

set_property IOSTANDARD LVCMOS18 [get_ports sys_rst]

If I understand your recommend well,

 

I've got the below messages

[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. The GTXE_COMMON component can use the dedicated path between the GTXE_COMMON and the GTXE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/k7_v7_gtxe2_common_inst/O1] >

	srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/k7_v7_gtxe2_common_inst/gtxe2_common_0_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y0
	 srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/srio_gen2_0_inst/inst/srio_gt_wrapper_inst/inst/srio_gen2_0_i/gt0_srio_gen2_0_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y5

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_bufds_bufg
	Status: PASS 
	Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device
	 srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
	 srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/srio_clk_inst/refclk_bufg_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1

	Clock Rule: rule_bufds_gtxchannel_intelligent_pin
	Status: PASS 
	Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region
	(top/bottom)
	 srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
	 srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/srio_gen2_0_inst/inst/srio_gt_wrapper_inst/inst/srio_gen2_0_i/gt0_srio_gen2_0_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y5

	Clock Rule: rule_bufds_gtxcommon_intelligent_pin
	Status: PASS 
	Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
	(top/bottom)
	 srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/srio_clk_inst/u_refclk_ibufds (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
	 and srio_example_top_ip_srio_gen2_1_dsp_2/srio_support_inst/k7_v7_gtxe2_common_inst/gtxe2_common_0_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y0

 

 

What does "Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. " mean?

 

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Xilinx Employee
Xilinx Employee
1,418 Views
Registered: ‎10-19-2011

Re: A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

Jump to solution

Hi @love119,

 

is that really the only xdc in your design? Does the srio core not have its own xdc?

What happens if you comment out the constraints for the RX and TX pins?

 

I see from your code in the other post that you instantiate the same IP 3 times. How is the IP generated?

Is the shared logic included in the core or not? You might run into issues with the common block if all three cores have it included.

There is only one in the quad.

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Explorer
Explorer
1,989 Views
Registered: ‎03-08-2018

Re: A problem of SRIO. Cannot set LOC property of ports, Site location is not valid

Jump to solution

When I change the xdc as the below

#-----------------------------------------------------------------------------
#
# File name:    srio_gen2_0.xdc
# Rev:          3.2
# Description:  This module constrains the example design
#
#-----------------------------------------------------------------------------
######################################
#         Core Time Specs            #
######################################

create_clock -period 8.000 -name sys_clkp -waveform {0.000 4.000} [get_ports sys_clkp]
set_case_analysis 0 [list [get_pins -hierarchical *mode_1x]]

set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *ack_sync_reg1}]
#set_multicycle_path -from [get_pins *cfg_raddr_reg* -hierarchical] -to [get_pins *cfg_reg*rdata_reg* -hierarchical] 3
#set_multicycle_path -from [get_pins *cfg_raddr_reg* -hierarchical] -to [get_pins *cfg_reg*rdata_reg* -hierarchical] 2 -hold

################################################################################
######################################################
##       GT and other Pin Locations                  #
## NOTE: These pins need to be updated for device:   #
## "xc7k480tffg901-2"#
## Below LOC's are given as dummy LOC's and          #
## need to be updated by the user                    #
######################################################

##  set_property LOC GTXE2_CHANNEL_X0Y8 [get_cells -hier -nocase -regexp {.*/gt_wrapper_i/gt0_gt_wrapper_i/gt.e2_i}]
##
##
set_property PACKAGE_PIN AD5 [get_ports sys_clkn]
set_property PACKAGE_PIN AD6 [get_ports sys_clkp]
 

set_property PACKAGE_PIN 	AC8	[get_ports 	sys_clkp2		]
set_property PACKAGE_PIN 	AC7	[get_ports 	sys_clkn2		]
set_property PACKAGE_PIN 	U8	[get_ports 	sys_clkp3		]
set_property PACKAGE_PIN 	U7	[get_ports 	sys_clkn3		]


set_property PACKAGE_PIN U17 [get_ports sys_rst]

set_property PACKAGE_PIN AK6 [get_ports FPGA_SRIO0_TXP]
set_property PACKAGE_PIN AK5 [get_ports FPGA_SRIO0_TXN]
set_property PACKAGE_PIN AJ12 [get_ports FPGA_SRIO1_TXP]
set_property PACKAGE_PIN AJ11 [get_ports FPGA_SRIO1_TXN]
set_property PACKAGE_PIN AF2 [get_ports FPGA_SRIO2_TXP]
set_property PACKAGE_PIN AF1 [get_ports FPGA_SRIO2_TXN]

#set_property PACKAGE_PIN AJ4 [get_ports FPGA_SRIO1_TXP]
#set_property PACKAGE_PIN AJ3 [get_ports FPGA_SRIO1_TXN]
#set_property PACKAGE_PIN AK2 [get_ports FPGA_SRIO2_TXP]
#set_property PACKAGE_PIN AK1 [get_ports FPGA_SRIO2_TXN]

set_property PACKAGE_PIN AH6 [get_ports FPGA_SRIO0_RXP]
set_property PACKAGE_PIN AH5 [get_ports FPGA_SRIO0_RXN]
set_property PACKAGE_PIN AH10 [get_ports FPGA_SRIO1_RXP]
set_property PACKAGE_PIN AH9 [get_ports FPGA_SRIO1_RXN]
set_property PACKAGE_PIN AB6 [get_ports FPGA_SRIO2_RXP]
set_property PACKAGE_PIN AB5 [get_ports FPGA_SRIO2_RXN]

#set_property PACKAGE_PIN AG4 [get_ports FPGA_SRIO1_RXP]
#set_property PACKAGE_PIN AG3 [get_ports FPGA_SRIO1_RXN]
#set_property PACKAGE_PIN AE4 [get_ports FPGA_SRIO2_RXP]
#set_property PACKAGE_PIN AE3 [get_ports FPGA_SRIO2_RXN]

set_property IOSTANDARD LVCMOS18 [get_ports sys_rst]
                                                                    
#set_property LOC GTXE2_CHANNEL_X0Y4  [get_cells srio_example_top_ip_srio_gen2_1_dsp_1/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt0_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y5  [get_cells srio_example_top_ip_srio_gen2_1_dsp_1/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt1_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells srio_example_top_ip_srio_gen2_1_dsp_2/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt0_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells srio_example_top_ip_srio_gen2_1_dsp_2/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt1_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y8  [get_cells srio_example_top_ip_srio_gen2_1_dsp_3/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt0_srio_gen2_1_i/gtxe2_i]
#set_property LOC GTXE2_CHANNEL_X0Y9  [get_cells srio_example_top_ip_srio_gen2_1_dsp_3/srio_gen2_1_inst/inst/srio_gen2_1_block_inst/srio_gt_wrapper_inst/inst/srio_gen2_1_i/gt1_srio_gen2_1_i/gtxe2_i]


It's works. 

 

I have some question about this.

 

I see.. that should be assigned by generated SRIO logic setting. and I have to follow this rule. If I set 1 lane of 3 srio , then I have to use just *0 ports of 3 srio..

oh.. Thanks! now I understand what you are saying.

 

 

Now I have to resolve multi SRIO implementation in one Differential Clock source domain.

Actually I've the problem one more https://forums.xilinx.com/t5/7-Series-FPGAs/Can-I-make-3-differential-clock-from-1-differential-clock/m-p/846623#M26350

 

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