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fcaldi@92
Contributor
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Registered: ‎05-11-2018

Attribute values for ultrascale plus gty transceiver

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Hi,

    I'm trying to find values to be written in the DRP registers of the transceiver ultrascale plus gty in order to have a design running at multiple speed. Is it correct if I generate the transceiver macro for all the needed speeds and take the attribute values present in the simulation netlist file as values for the registers to be reconfigured through DRP?

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karnanl
Xilinx Employee
Xilinx Employee
368 Views
Registered: ‎03-30-2016

Hello fcaldi@92 

Yes, your understanding is correct. You need to generate transceiver macro for all line-rate use-cases.

No need to check for the netlist, please check the synthesis wrapper RTL instead.
( for example : project_name.srcs\sources_1\ip\gtwizard_ultrascale_0\synth\gtwizard_ultrascale_0_gtye4_channel_wrapper or gtwizard_ultrascale_0_gtye4_common_wrapper.v )
Just compare those files, you will see attributes with different values that you need to update using DRP I/F.

Thanks & regards
Leo

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karnanl
Xilinx Employee
Xilinx Employee
369 Views
Registered: ‎03-30-2016

Hello fcaldi@92 

Yes, your understanding is correct. You need to generate transceiver macro for all line-rate use-cases.

No need to check for the netlist, please check the synthesis wrapper RTL instead.
( for example : project_name.srcs\sources_1\ip\gtwizard_ultrascale_0\synth\gtwizard_ultrascale_0_gtye4_channel_wrapper or gtwizard_ultrascale_0_gtye4_common_wrapper.v )
Just compare those files, you will see attributes with different values that you need to update using DRP I/F.

Thanks & regards
Leo

View solution in original post

fcaldi@92
Contributor
Contributor
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Registered: ‎05-11-2018

Thanks for the reply @karnanl . I've done a fast comparison between the simulation netlist file and the wrapper of the gty channel and at the end they seems to equivalent for the section related to attributes. So using one or the other to retrieve information seems the same.