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Visitor joao_banana
Registered: ‎07-31-2018



I'm a masters student and doing some work related to NGPON-2 for my thesis. I'm using a Kintex Ultrascale 105 - part: K040-ffva1156-2e. So far, the current project consists on feeding information through an MGT (Tx: 32bits at 10G  and Rx: 32b at 10G with no coding(ie. Raw))  looping it into the board and detecting those frames with the same block that sent them.

In order to implement correctly burst mode operation, I understand that I need to use the BCDR blocks. I have looked into XAPP1252,XAPP1277 and XAPP1083 but I still dont get some details:

1- Is it possible to create the described design? Is something missing? 

2 - What are the differences between the independent BCDR block(from XAPP1277) and the BCDR-QuickLock-Circuit(from XAPP1252) ? 

3 - On the BCDR block: am I limited to the two cases: 80bits In and 32Bits Out or 32bits In and 8bits Out

4 - This output of BCDR block, is always smaller than the input. But does it actually mean or show? A fragment of the input frame or something else? Because on the refference design it is connected directly to the pattern checker. And so the ouput named DV_OUT means that DT_OUT is valid, but valid in which way? 

Thank you for your time and I hope I made my questions clear to you.
Kindest Regards, 


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Xilinx Employee
Xilinx Employee
Registered: ‎11-29-2007


hello Joao,

the two applications, XAPP1277 and XAPP1252 are completely different.

XAPP1277 is an oversampling based solution. The receiver is acting as an oversampler, its CDR unit is frozen, and the fast lock to preamble and data is achieved thanks to a smart usage of a Non Integer Data Recovery Unit (NIDRU). For clarity, the NIDRU takes all samples and extracts those sitting in the middle of the UI. You might study as reference XAPP875.

Even if this method is able to acquire signal lock with an unmatched speed, in order to have this solution functional we need many samples per each UI, thus the signal datarate cannot be too high. This solution can be good for example for a 2.5Gbps case.

Vice versa, for example in the case of a 10Gbps as you are planning to run your design, the other XAPP1252 leverage on a completely different mechanism: here the CDR is functional, free to follow the signal. The trick to achive a deterministic max locking time is to probe the CDR phase evolution, and if it remains too much in a metastable condition, artificially move away from that equilibium point.


Visitor joao_banana
Registered: ‎07-31-2018


Oh, I think I understand. Thank you very much, I will look into the BCDR-QuickLock circuit through the XAPP1252
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