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adam_mira
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Registered: ‎01-13-2020

CDR circuit parameter - PPM offset between receiver and transmitter

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Hi,

Ultrascale GTH transceiver:

1. From the transceiver wizard, the parameter "PPM offset between receiver and transmitter"  is parameter input to the CDR circuit only. Correct? If so, how it is used? The relevant documents don't contain information regarding this topic. (PG182 , PG576)

2. The parameter "PPM offset between receiver and transmitter" has something to do with the Receiver clock correction mechanism?

3. I have received a GTH3_CHANNEL instantiation pre-configured to a specific protocol. (i.e. a VHDL file with all the generics and ports)  I'm trying to figure out from that file what is the "PPM offset between receiver and transmitter" parameter setting for that GTH3_CHANNEL. Is that possible? if so, how? and can I modify this parameter directly from the file?

 

Thank you!

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roym
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Registered: ‎07-30-2007

If the far end and near end are rooted to the same oscillator the frequency offset (PPM) will be 0 and you can see this on a scope by looking at the txoutclk and the RXOUTCLK from the pma (this is the recovered clock).  You should see they are locked and don't drift wrt to each other.  You should probably know already if there is a refclk connection from the far end device to your device and this won't be necessary.

Rooted to the far end oscillator means driven in one manner or another by the far end oscillator.  It may have dividers, PLL's or clock muxes in the path but the key is it is driven by the far end oscillator and will be in sync with it.

What you will have to do is use the GT wizard to make example design at your line rate and data width and change PPM parameters (PPM setting is on lower half of the first page of the wizard.)  Then you can synthesize the designs and export the attributes for that design.  If you make 3 designs with PPM set to 0, 100, 200 there is a high probability that one of the 3 will have the CDR settings you are looking for.  Start with 200 as it is probably the right one.  These attributes don't typically change a lot from one PPM to the next so you may find PPM 100 is the same as 200.  It usually takes 5 to 10 minutes to make and synthesize a design like this.




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roym
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Registered: ‎07-30-2007

1.  It is used to set the CDR's PLL loop parameters that work best with the PPM that will be used.  In any phase locked loop there is a trade-off between how tightly the loop can be locked and what range of frequencies can be locked.  The PPM gives us information on the range of frequencies that need to be locked and the attributes are adjusted accordingly.   The documents don't contain detailed information on this because it is considered proprietary.  

2.  PPM has to do with the CDR lock mechanism and setting the attributes for the best result.  Clock correction is a way to correct the difference in frequencies between the recovered clock and the reference clock.  The recovered clock is clocking data into the RX buffer.  In most cases these days the recovered clock will also drive the RXUSRCLK that clocks data out of the RX buffer.  In this case no clock correction is needed.  In cases where the reference clock with a PPM difference to the recovered clock drives the RXUSRCLK clock correction is needed to correct for that PPM offset.

3.  The PPM offset is calculated and set in the GT wizard.  You should be able to open the *.XCI file for your GTH channel to see what the PPM is set to.  In any case you need to know what the PPM is in the system you are designing for.  You should be able to determine that from the specs of the refclk oscillators involved.




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adam_mira
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@roym Thank you for the answer!

About Q3, what if I don't have the .xci file? (It's not hypothetical, I don't have it...) I only have the gth_channel instantiation. (The files from the IP's synth folder) 

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roym
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Registered: ‎07-30-2007

The *.xci file isn't the only file that contains this.  Do a "find in files" on PPM_OFFSET in your project directory.  If this doesn't yield information you'll have to try to recreate it.  You can measure in your system to see whether the PPM is 0 (rooted to the far end refclk oscillator).  Otherwise a setting of 200 PPM will likely suffice.  You will have to try different values of PPM until you see no difference in the *CDR_CFG* attributes.  You can open the synthesized design checkpoint for the GT and see how these parameters are set in the properties window.  In the properties window of the GT you could export all the attributes to a file and then compare the files to see attribute differences.




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adam_mira
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Do a "find in files" on PPM_OFFSET in your project directory.
- It didn't yield any results.

You can measure in your system to see whether the PPM is 0 (rooted to the far end refclk oscillator).
- What do you mean by "measure"? What rooted to the far end refclk oscillator?

You will have to try different values of PPM until you see no difference in the *CDR_CFG* attributes
- How can I change the value of the PPM? The related attributes/properties names are "RXCDR_CFG0" ,"RXCDR_CFG1", ... , "RXCDR_CFG5". I can't figure out how to change them.

You can open the synthesized design checkpoint for the GT and see how these parameters are set in the properties window.  In the properties window of the GT you could export all the attributes to a file and then compare the files to see attribute differences.
I see the properties window. The missing piece of the puzzle: how to change the PPM setting to see the change impact in the properties?

Thank you for your support @roym !

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roym
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Registered: ‎07-30-2007

If the far end and near end are rooted to the same oscillator the frequency offset (PPM) will be 0 and you can see this on a scope by looking at the txoutclk and the RXOUTCLK from the pma (this is the recovered clock).  You should see they are locked and don't drift wrt to each other.  You should probably know already if there is a refclk connection from the far end device to your device and this won't be necessary.

Rooted to the far end oscillator means driven in one manner or another by the far end oscillator.  It may have dividers, PLL's or clock muxes in the path but the key is it is driven by the far end oscillator and will be in sync with it.

What you will have to do is use the GT wizard to make example design at your line rate and data width and change PPM parameters (PPM setting is on lower half of the first page of the wizard.)  Then you can synthesize the designs and export the attributes for that design.  If you make 3 designs with PPM set to 0, 100, 200 there is a high probability that one of the 3 will have the CDR settings you are looking for.  Start with 200 as it is probably the right one.  These attributes don't typically change a lot from one PPM to the next so you may find PPM 100 is the same as 200.  It usually takes 5 to 10 minutes to make and synthesize a design like this.




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
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----------------------------------------------------------------------------


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adam_mira
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Registered: ‎01-13-2020

In my case, the far end connects to the near end only with the data lines. There is not a common oscillator. On top of that, I can not measure the clocks using external instruments because I physically don't have access to the clocks (i.e. the clock's copper lines).

The good news is that the GT wizard "try and error" led me to the correct setting (I believe so) and the incoming data seems to be correct now. 
The CDR lock indication is still not stable but from other posts I've seen you commented on, I understand that It's OK as long as the incoming data is correct.

I am working now on checking the incoming data because the source does not support the easy check of PRBS pattern.

@roym, thank you for your help and guidance!

Adam 

 

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