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alexis_jp
Explorer
Explorer
698 Views
Registered: ‎09-10-2019

Can I safely connect TXOUTCLK of a channel to TXUSRCLK of 2-3-4 GTY channel modules?

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I'd like to use the same TX user clock to drive two instances of the same GTY module located in the same QUAD connected to the same QPLL (QPLL0) with TX/RX buffer bypass.

The GTY common is shared among the 4 channels of the quad.

UG578 - Using TXOUTCLK to Drive the TX Interface

alexis_jp_0-1604484392661.png

There is a note regarding the TX phase alignment circuit, does it mean I can't use that clock for a different channel?

  • Can I safely connect TXUSRCLK/2 of both gty channels from one of the 2 TXOUTCLK?

If not, what's the best practice to use the same TX clock generated by one of the two (up to 4) GTY channels?

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karnanl
Xilinx Employee
Xilinx Employee
682 Views
Registered: ‎03-30-2016

Hello @alexis_jp 

I don't see any issue on this case.
I assumed that all GTY channel has the same configuration.

Thanks & regards
Leo


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Don’t forget to reply, kudo, and accept as solution.
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2 Replies
karnanl
Xilinx Employee
Xilinx Employee
683 Views
Registered: ‎03-30-2016

Hello @alexis_jp 

I don't see any issue on this case.
I assumed that all GTY channel has the same configuration.

Thanks & regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

alexis_jp
Explorer
Explorer
646 Views
Registered: ‎09-10-2019

@karnanl 

Exactly they have the same configuration.

That's perfect, thank you!

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