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Registered: ‎05-22-2018

Cannot observe txoutclk signal from JESD204 PHY IP for bitstream generated design; cannot observe clock signals

Hi everyone,

Cannot observe txoutclk signal from JESD204 PHY IP for bitstream generated design

I am feeding the reference clock to cpll_refclk and qpll0_refclk ports of JESD204 PHY block. I observed the gt_cplllock[N-1:0] lines and all of them are high. However I do not see the clock signal at txoutclk port of JESD204 PHY block.

 

cannot observe clock signals([DRC-RTSTAT-2] error)

I am also trying to monitor some of the debug signals and other clk signals from the same IP such as common0_qpll0_clk_out and common0_qpll0_refclk_out by making them external. I set the IOSTANDARD constraint of the pins to that of the physical GPIO pins I want to monitor them at, followed by the PACKAGE_PIN constraint as following

 

set_property IOSTANDARD LVCMOS33 [get_ports common0_qpll0_clk_out_0]
set_property PACKAGE_PIN G16 [get_ports common0_qpll0_clk_out_0]

 

I am unable to generate bitstream. I most commonly get [DRC-RTSTAT-2] error when I try this.

I am using Vivado 2018.2

 

Can someone suggest what can be done to resolve both issues?

 

Thanks in advance,

 

 

-krishnachandrasekhar100

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Registered: ‎07-30-2007

Those 2 ports common0_qpll0_clk_out  signals can only drive the GT*_CHANNEL.  They are internal signals on fixed routing.  They can go to multiple GT*CHANNELs but they cannot go to output pins.

The refclk input pin must first go through an IBUFDS_GTE* before going to one of the refclk input pins.  I am not completely familiar with the JESD phy IP but I think there should be an example design that will show the proper connections.  If not you can just do an ordinary transceiver example design and see how the cpll and the Qpll are connected.  It is fixed internal routing.  There are options but not many.  I don't think you said the family but they are all similar in this respect you can see on page 32 and 33 of UG576 the pins that the output of the IBUFDS_GTE* can drive.

These are connections that the example design will normally connect for you and if you use the example design as a starting point and modify it's inputs and outputs to your needs it should be easier.




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Registered: ‎05-22-2018

Hi @roym ,

 

So what is the use of common0_qpll0_clk_out and common0_qpll0_refclk_out? In what case are they used, can you elaborate? When does the case arise when they need to go to GT channels?

I am ensuring that the differential input refclk is going through IBUFDS_GTE4 (ultrascale+), giving out a single ended clock signal, which is then given to cpll and qpll0 of JESD204 PHY block. So do you say that this txoutclk cannot be routed to maybe an LED(masking it external and assigning it to an LED)? I would prefer for it to be mapped to one of the GPIO pins available on the board though. Is either of them possible?

 

Can you give your suggestions here?

 

Thanks in advance,

 

-krishnachandrasekhar100

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