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Registered: ‎09-14-2019

Clock Forwarding with ODDR on the ZCU102 from SMA GT Clk Pins to Si5328 - Lots of noise?

Hi, so I've recently been attempting to forward a 1MHz clock from the SMA GT inputs on a ZCU102 board to the on board SI5328 CLK1 inputs to attenuate jitter on a clock source, but I've been facing problems getting the Si5328 to sync. I've meticulously reviewed the register settings which I've programmed the jitter attenuator/multiplier with via I2C and reviewed Si's documentation along with the notes provided here (granted in this individual's case they're using the on board third overtone crystal rather than an external clock source... Still very helpful notes):

This lack of lock was odd to me until I sent a couple signals out for viewing on a scope. The buffered clock signal is getting random noise on the line unexpectedly that isn't coming from the clock source; this leads me to believe the Si5328 is therefore unable to lock on to the buffered source. I'd normally just assume the input clock is just dirty/jittery, but I have trouble with assuming this because there are artifacts that downright look like misconstrued edges. Here's a picture of the scope output here(Yellow Channel is the clock source and the blue channel is the noisy output; I'm also aware the trigger on the scope is relatively high in the picture, but placement of the trigger isn't affecting these artifacts):


Could this be CDR noise that I've read a lot about? Doubtful because I'm not using a transceiver, so there is no CDR module. All the while this is very odd to me and renders this clock signal rather useless. This makes me think that my routing scheme is probably misinformed.

As such I've drawn up a schematic detailing my routing and included a copy of my VHDL code and the general pin constraints. Have I just set this up incorrectly or are there some timing constraints that are necessary that I'm unaware of? Any help in cleaning this up would be greatly appreciated!



My constraints follow:


#create_clock -period 10.000 -name MGTCLK_P -waveform {0.000 5.000} [get_ports MGTCLK_P]
create_clock -period 1000.000 -name SMA_REF_IN_P [get_ports SMA_REF_IN_P]

set_property PACKAGE_PIN B9 [get_ports MGTCLK_N]
set_property PACKAGE_PIN B10 [get_ports MGTCLK_P]

set_property PACKAGE_PIN J28 [get_ports SMA_REF_IN_N] ;# Bank 129 - MGTREFCLK1N_129
set_property PACKAGE_PIN J27 [get_ports SMA_REF_IN_P] ;# Bank 129 - MGTREFCLK1P_129

#SI5328 Reference Clock out
set_property PACKAGE_PIN R9 [get_ports SI5328_CLK1_N]
set_property IOSTANDARD LVDS [get_ports SI5328_CLK1_N]
set_property PACKAGE_PIN R10 [get_ports SI5328_CLK1_P]
set_property IOSTANDARD LVDS [get_ports SI5328_CLK1_P]

set_property PACKAGE_PIN AE14 [get_ports "PUSHBUTTON_RST"] ;# Bank 44 VCCO - VCC3V3 - IO_L12N_AD0N_44
set_property IOSTANDARD LVCMOS33 [get_ports "PUSHBUTTON_RST"] ;# Bank 44 VCCO - VCC3V3 - IO_L12N_AD0N_44

set_property PACKAGE_PIN J15 [get_ports "SI5328_OUT_PIN"] ;# Bank 50 VCCO - VCC3V3 - IO_L12N_AD8N_50
set_property IOSTANDARD LVCMOS33 [get_ports "SI5328_OUT_PIN"] ;# Bank 50 VCCO - VCC3V3 - IO_L12N_AD8N_50
set_property PACKAGE_PIN J16 [get_ports "SMA_BUF_REF_PIN"] ;# Bank 50 VCCO - VCC3V3 - IO_L12P_AD8P_50
set_property IOSTANDARD LVCMOS33 [get_ports "SMA_BUF_REF_PIN"] ;# Bank 50 VCCO - VCC3V3 - IO_L12P_AD8P_50

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2 Replies
Registered: ‎09-14-2019

Replying to share that after viewing directly out from the BUFG_GT module over the scope, the noise is still apparent. Does this then imply that the noise I'm seeing is likely coming from the GTE4 primitive?

Pic below:



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Registered: ‎01-22-2015


Thanks for careful and clear explanation of your setup and the problem.

The "noise" you are seeing looks like glitching at the MGTREFCLK1 input to the FPGA.  Please check that your external clock meets specifications for a Reference Clock as described starting on page 325 of UG576(v1.6).  UG576 will refer you to the datasheet, DS925(v1.18), for the XCZU9 FPGA on the ZCU102 board.  

Also, using your scope, zoom in on edges of both SMA_REF_IN_P and SMA_REF_IN_N to ensure that they meet the rise/fall time (TRCLK / TFCLK) specifications for a Reference Clock and are glitch-free.



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