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Participant
Participant
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Registered: ‎07-10-2018

Clock question about jesd204 core simulation

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Hello.

Now I simulate the JESD204 ip core in Vivado 2015.4. I find in the demo_tb.v, The period of refclk0 and glblclk is 5.04ns(198.4MHz),which is not matching with the value(200MHz) setted in JESD204 IP UI. And when I change the period of refclk0 and glblclk to 5ns, the sync signal can not be pulled up in simulation.

I want to know what is the reason of the problem? Should I use the 198.4MHz as refclk0 and glblclk in hardware implemention?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @zhikai ,

please use 200MHz in your hardware.

In the simulation are just slightly different frequency values used to have the clocks asynchronous. It is 5ns used for the drpclk and 5.04ns for the refclk as far as I can see in a 2019.1 simulation.

You mention you use 2015.4. This is a bit older version. Would you be able to update to 2019.1?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @zhikai ,

please use 200MHz in your hardware.

In the simulation are just slightly different frequency values used to have the clocks asynchronous. It is 5ns used for the drpclk and 5.04ns for the refclk as far as I can see in a 2019.1 simulation.

You mention you use 2015.4. This is a bit older version. Would you be able to update to 2019.1?

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Participant
Participant
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Registered: ‎07-10-2018

Hi @eschidl ,

It is also 5.04ns for the refclk in 2015.4, which is the same value with 2019.1. And I found the reason why when I changed the value of refclk to 5ns, the sync signal can not be pulled up in simulation.

Users should change the delay value in the task "rx_stimulus_send_10b_column" to #125 from #126 after they changed the refclk value to 5ns, and then the sync signal can be pulled up.

Thanks!

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