Dependency of DRP clock speed on user data width

[evgenis1]

Hello,

I want to understand why there is a dependency of DRP clock speed on user data width. For example, in Ultrascale+ GTY transceiver wizard, max DRP frequency is 62.5mhz for 40-bit user data width, or 31.25mhz for 80-bit data width. 

DRP clock is supposed to be free-running, and independent of anything else.

Documentation doesn't say anything about that. Switching characteristics document specifies max DRP clock frequency of 250mhz.

Thanks,

Evgeni

[travisc · Accepted solution]

This is a rules check imposed by the wizard based on the free running clock maximum frequency. The Free running clock is the DRP clock, and its relationship is listed on page 10 of PG182. Essentially double the width, cuts the clock in half, just like the GUI shows.

https://www.xilinx.com/support/documentation/ip_documentation/gtwizard_ultrascale/v1_1/pg182-gtwizard-ultrascale.pdf