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Zoro100
Explorer
Explorer
733 Views
Registered: ‎05-22-2018

Equivalent block design for the example design of JESD TX

Hi everyone,

 

I see that example IP designs can be accessed for Xilinx IP in Vivado. However is there a way to create an example project with block design for it? In this case, for the JESD204 IP. I am using Vivado 2018.2 and it is for ZYNC Ultrascale+ that I search this example design for. 

 

I was able to simulate the example design with project generated for ZYNC Ultrascale+ However the bitstream failed and hence block diagram view would be better to figure out what constraints to place to generate the bitstream. I see too many s_axi debug ports on for JESD204 IP related errors, while generating bitstream.

 

Can someone suggest what can be done?

 

Thanks in advance,

 

 

-krishnachandrasekhar100

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roym
Moderator
Moderator
693 Views
Registered: ‎07-30-2007

If you have IP in a block design you should still be able to right click on it and select "open example design".  




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Zoro100
Explorer
Explorer
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Registered: ‎05-22-2018

Hi @roym ,

 

I just imported JESD204 IP into my project, customized it and am trying to open example project. The resultant example project does not come as a block diagram and hence not encouraging any modifications to it at the block design level. Need to change the verilog code in files instead.

Hence I was asking if the example designs for IPs can come in block designs.

 

-krishnachandrasekhar100

 

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eschidl
Xilinx Employee
Xilinx Employee
641 Views
Registered: ‎10-19-2011

Hi @Zoro100 ,

this would depend on the IP how this is setup. You cannot choose in what way the example design is presented.

The JESD204B IP generates its example design not in a block design.
The new JESD204C IP (which can also work in 8B10B mode) does generate its example design in a block design. But you might need to update to a newer Vivado version. Maybe the soon released 2020.2.

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Zoro100
Explorer
Explorer
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Registered: ‎05-22-2018

Hi @eschidl  ,

 

So I am kind of new to this JESD stuff. Let us say if I could work with vivado 2020.2, do you think looking at the block diagram, I should be able to implement the same on vivado 2018.2? What I am asking is, can I take the example design from 2020.2 to be a reference to build the same from scratch on vivado 2018.2?

This is important, for the sake that, we have only vivado 2018.2 with us and it will take time to fully upgrade to newer version. However, we can temporarily try and work on 2020.2 as the block design example is more important for us currently.

 

Edit: So I missed to notice 2020.2 is not out yet. Does the vivado 2020.1 version feature JESD204C IP and generate example as a block design?

 

So this option of generating examples as block design is for all IPs in 2020.2 (and in 2020.1)? Can you clarify this?

 

Thanks in advance,

 

 

-krishnchandrasekhar100

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eschidl
Xilinx Employee
Xilinx Employee
583 Views
Registered: ‎10-19-2011

Hi @Zoro100,

you could of course use the block design of the JESD204C core as an example to build a block design for the JESD204B core. But there are differences between the IPs. You will need to adjust to this.

The JESD204C core is already available in 2018.2 and generates the example design as a block design as well. It is just still a pre-production version. This will be different in 2020.2. There were several changes done to the IP.

As said before, it depends on the IP development if the example design will be generated in a BD or not. This is not dependent on the Vivado version.

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