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1,317 Views
Registered: ‎11-25-2017

GTH LOC issue on Kintex Ultrascale

Hi,

I am trying to build a Interface for AD9371 (2 TX 2 RX)  RF driver with JESD PHY cores on Kintex Ultrascale FPGA (xcku060-ffva1156-2-e). When I am trying to do a build, I am getting the LOC related Critical warning. I am able to generate the Bit file but with warnings. Is there a way to bypass this issue or overcome.

Below is the pin constraints used for TX and RX data paths. These pins are located on Bank 228. 

 

 

10 - set_property -dict {PACKAGE_PIN D2 } [get_ports rx_data_p[0]]
11 - set_property -dict {PACKAGE_PIN D1 } [get_ports rx_data_n[0]]

13 - set_property -dict {PACKAGE_PIN B2 } [get_ports rx_data_p[1]]
14 - set_property -dict {PACKAGE_PIN B1 } [get_ports rx_data_n[1]]

16 - set_property -dict {PACKAGE_PIN E4 } [get_ports rx_data_p[2]]
17 - set_property -dict {PACKAGE_PIN E3 } [get_ports rx_data_n[2]]

19 - set_property -dict {PACKAGE_PIN A4 } [get_ports rx_data_p[3]]
20 - set_property -dict {PACKAGE_PIN A3 } [get_ports rx_data_n[3]]

22- set_property -dict {PACKAGE_PIN C4 } [get_ports tx_data_p[0]]
23 - set_property -dict {PACKAGE_PIN C3 } [get_ports tx_data_n[0]]

25 - set_property -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[1]]
26 - set_property -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[1]]

28 - set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[2]]
29 - set_property -dict {PACKAGE_PIN B5 } [get_ports tx_data_n[2]]
31 - set_property -dict {PACKAGE_PIN D6 } [get_ports tx_data_p[3]]
32 - set_property -dict {PACKAGE_PIN D5 } [get_ports tx_data_n[3]]

 

I have mentioned the line numbers also so that it will be easy to relate to the warnings with respect to line numbers in the XDC file. I am attaching the image of warning I have got.

LOC_warning_KCU060.png
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7 Replies
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Moderator
Moderator
1,256 Views
Registered: ‎07-30-2007

Re: GTH LOC issue on Kintex Ultrascale

When you run the GT wizard you select the location of the GT Channel instances.  The wizard will then put Loc instances in an XDC file for your design.  If you come along later and try to move the instances that you selected in the wizard by setting output pin constraints the 2 sets of constraints will clash and you will have the kind of errors shown below.  If you set the positions correctly in the wizard you don't need any loc constraints on the rx and tx data ports.




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Observer
Observer
671 Views
Registered: ‎12-20-2018

Re: GTH LOC issue on Kintex Ultrascale

Hi Roy,

 

Can you let me know how to fix the locations to the ones I need?

I have the required placement in the below order:

GTHE3_CHANNEL_X1Y15 - Lane 3
GTHE3_CHANNEL_X1Y14 - Lane 2
GTHE3_CHANNEL_X1Y13 - Lane 1
GTHE3_CHANNEL_X1Y12 - Lane 0

But I want it in this configuration

GTHE3_CHANNEL_X1Y15 - Lane 3
GTHE3_CHANNEL_X1Y14 - Lane 1
GTHE3_CHANNEL_X1Y13 - Lane 0
GTHE3_CHANNEL_X1Y12 - Lane 2

It ignores my placement constraints and does this by default.

Regards,
Sundar

 

Capture.PNG
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Xilinx Employee
Xilinx Employee
636 Views
Registered: ‎08-07-2007

Re: GTH LOC issue on Kintex Ultrascale

hi @sundarbas 

 

you can locate the <component_name>_gt.xdc and modify the GT_CHANNEL LOC constraints by using a text editor.

 

Thanks,

Boris

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Observer
Observer
624 Views
Registered: ‎12-20-2018

Re: GTH LOC issue on Kintex Ultrascale

Hi Boris,

Thank you for your comment.

This does work. But do you have any deterministic permanent solution to this? I fear that if I was to regenerate/modify my IP core, the old constraints will creep back in and produce more issues in my system.

I tried to change the order to read my User XDC after IP constraints and vice versa and they both didnt work.

 

Sundar

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Highlighted
Moderator
Moderator
615 Views
Registered: ‎07-30-2007

Re: GTH LOC issue on Kintex Ultrascale

I think a more repeatable solution is to just reorder the RXDATA*[] and TXDATA*[] inputs and outputs from the GT_CHANNEL to your code to match the order you desire.  Stay with the wizard location for placing the GT_channel. 




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Observer
Observer
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Registered: ‎12-20-2018

Re: GTH LOC issue on Kintex Ultrascale

The problem is I do run simulation in another environment and it might create an issue there.

I wish there was configurability from within the wizard to specify which lanes go where, or proper override for the constraints.

 

Are you aware of any specifiers to override pre-existing constraint with the new constraint I am providing now?

 

Regards,

Sundar

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Xilinx Employee
Xilinx Employee
590 Views
Registered: ‎08-07-2007

Re: GTH LOC issue on Kintex Ultrascale

hi @sundarbas 

 

you can have a look at UG896 Page 108 about Editing IP Sources.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug896-vivado-ip.pdf

 

Thanks,

Boris

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