UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
162 Views
Registered: ‎01-17-2018

GTH REFCLK issue in KCU105

 

Hi,

I am Using KCU105 Evaluation board. I am generating 120MHz ref clk(differential) from SI570 on the board and converting it into single ended clk using IBUFDS_GTE3. Now  i am driving this single ended clk to GTH IP core (as gtrefclk) as well as OBUFDS_GTE3. Using OBUFDS_GTE3 i am again converting the single ended into differential, so that i can transmit out the differential clock through GTH USER_SMA (J33 & J32).

During this operation i am getting the DRC REQP-1847 error as follows.

[DRC REQP-1847] IBUFDS_GTE3_O_may_only_drive_GTxE3: The IBUFDS_GTE3 IBUFDS_GTE3_XCVR_REF_CLK O pin may only be connected to the GTREFCLK pin of a GTHE3_COMMON, GTHE3_CHANNEL, GTYE3_COMMON, or GTYE3_CHANNEL component. The IBUFDS_GTE3 O pin cannot drive OBUFDS_GTE3_inst, and ace_serdes/inst/gen_gtwizard_gthe3_top.gtwizard_ultrascale_0_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST.

I tried it in different ways but it doesn't resolved.

Please help me to resolve the issue.

Thank you

0 Kudos
11 Replies
156 Views
Registered: ‎01-17-2018

Re: GTH REFCLK issue in KCU105

 

Hi,

The code i am using is:

IBUFDS_GTE3 # (
  .REFCLK_EN_TX_PATH (1'b0),
  .REFCLK_HROW_CK_SEL (2'b00),
  .REFCLK_ICNTL_RX (2'b00) 
) IBUFDS_GTE3_XCVR_REF_CLK (
    .I (MGT_SI570_CLOCK_C_P),
    .IB (MGT_SI570_CLOCK_C_N),
    .CEB (1'b0),
    .O (xcvr_ref_clk),
    .ODIV2 ()
);

and 

OBUFDS_GTE3 #(
  .REFCLK_EN_TX_PATH(1'b1),
  .REFCLK_ICNTL_TX(5'b00000)
)
OBUFDS_GTE3_inst (
    .I(xcvr_ref_clk),
    .CEB(1'b0),
    .O(user_SMA_clk_P_J33),
    .OB(user_SMA_clk_N_J32)
);

and i am using the "xcvr_ref_clk" as "gtrefclk" in the GTH ip core

.gtrefclk0_in                      (xcvr_ref_clk),

May I use like this?

If not how can i connect?

0 Kudos
Xilinx Employee
Xilinx Employee
145 Views
Registered: ‎10-19-2011

Re: GTH REFCLK issue in KCU105

Hi c.gannamani@gmail.com,

please have a look at ug576, page 22, first paragraph where it says: "In the output mode of operation, the recovered clock (RXRECCLKOUT) from any of the four channels within the same Quad can be routed to the dedicated reference clock I/O pins."

So the routing you have in mind is not possible as you want to drive the reference clock out and not the recovered one.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
107 Views
Registered: ‎01-17-2018

Re: GTH REFCLK issue in KCU105

Hi Eschidl,

Thank you so much for your response and information.

So, I will try with RXRECCLKOUT.

0 Kudos
Xilinx Employee
Xilinx Employee
95 Views
Registered: ‎10-19-2011

Re: GTH REFCLK issue in KCU105

Hi c.gannamani@gmail.com,

please be aware that you have the CDR noise on that clock.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
92 Views
Registered: ‎01-17-2018

Re: GTH REFCLK issue in KCU105

 

Hi Eschidl,

Now the bit file is generated using RXRECCLKOUT. But I am not able to measure the frequency value of RXRECCLKOUT using scope. I am providing 120MHz differential clock as MGTREFCLKP/N and the dividers settings are RXSYSCLKSEL=00, REFCLKSEL=1, RXPLLCLKSEL=00,RXOUTCLKSEL=1 and RXDLYBYPASS= 1. 

Data rate is 6.0 Gbps so TXOUTCLK is 300MHz.

Using OBUFDS_GTE3 i am transmitting the RXRECCLKOUT  to J33 & J32 and measuring on 350MHz scope.

Can you guide how to measure the freq of RXRECCLKOUT?

 

0 Kudos
63 Views
Registered: ‎01-17-2018

Re: GTH REFCLK issue in KCU105

 

Hi,

Please provide the solution.

 

Thanks

Krishnachaitanya

0 Kudos
Xilinx Employee
Xilinx Employee
48 Views
Registered: ‎10-19-2011

Re: GTH REFCLK issue in KCU105

Hi c.gannamani@gmail.com,

do I see this right that you provide the 120MHz refclk through quad 227, either by using si570 or si5328?

And the transceiver you use is in quad 226.

Do you have a signal connected to the RX input of the transceiver?

Did the RX finish its reset sequence and you receive the expected data?

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
40 Views
Registered: ‎01-17-2018

Re: GTH REFCLK issue in KCU105

 

Hi Eschidl,

I am providing the 120MHz refclk from SI570 and using quad X0Y0 as shown in attachment.

 

Now i am able to measure the RXRECCLKOUT after enabling the RXRECCLKOUT buffer to MGTREFCLK1 as shown in attached figure.

I modified another primitive value REFCLK_ICNTL_TX(5'b00000)  to REFCLK_ICNTL_TX(5'b00111) .

gth_refclk_usage.PNG

0 Kudos
39 Views
Registered: ‎01-17-2018

Re: GTH REFCLK issue in KCU105

Hi Eschidl,

 

Thank you so much for your support.

Regards 

Krishnachaitanya

0 Kudos
Xilinx Employee
Xilinx Employee
26 Views
Registered: ‎10-19-2011

Re: GTH REFCLK issue in KCU105

Hi c.gannamani@gmail.com,

I am not sure what you actually see on the SMA ports.
From your picture you selected only bank 224 for your setup. The refclks of bank 224 are not connected on kcu105.
The SMA connectors bring out refclk0 of bank 226.
And refclk1 of bank 226 is connected to a FMC port and not si570.

Can you explain?

Also, the attribute you mentioned is reserved. I do not have information what this attribute is doing. Why do you change it?

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
6 Views
Registered: ‎08-07-2007

Re: GTH REFCLK issue in KCU105

hi c.gannamani@gmail.com

 

I see you select Bank 224 MGTREFCLK0 as input and Bank 224 MGTREFCLK1 as output.

I'm afraid this may not work on KCU105 eval board because Bank 224 MGTREFCLK0 and MGTREFCLK1 are NC (not connected). 

 

If you want to use SI570 clock as GT reference clock, you can use Bank 227 MGTREFCLK0.

If you want to output the reference clock and probe the reference clock by a scope, you do this:

connect the ODIV2 output of IBUFDS_GTE3 to a BUFG_GT, connect the BUFG_GT to an ODDR (or OSERDES), and connect ODDR output to OBUFDS, and output pin pairs (USER_SMA_GPIO_P, USER_SMA_GPIO_N: J36, J37).

 

Thanks,

Boris

 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos