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Participant
Participant
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Registered: ‎02-23-2018

GTH Transceiver Wizard CPLL problem

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Hey guys, i am trying to make 2 separate trasnceiver wizards work (on Ultrascale+, ZCU102). Both should work independently, but share the reference clock. Both are also in the same QuadX1Y2 (see pictures).

Now my problem is the following: if i just generate a bitstream using just either one of the transceivers, everything works fine. But as soon as i use both, none of them work anymore. With ILA i could see that powergood goes up, but CPLL's won't lock anymore.

I also used Simulation to verify my design, everything works perfectly. 

What could be the problem? Is it a routing issue, because 2 seperate Wizards share the reference clock? or anything else???

Please help

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Participant
Participant
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Registered: ‎02-23-2018

Re: GTH Transceiver Wizard CPLL problem

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I solved my problem. Apparently it was due to wrong reset behaviour. Additionally for GTH transceivers, make sure to use the calibration block if you intend to change line rates (Xilinx AR 70485). After caring about these things, i could get the CPLL of 2 separate transceiver wizards to work.

Thanks for all of your help!

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Moderator
Moderator
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Registered: ‎07-30-2007

Re: GTH Transceiver Wizard CPLL problem

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Each example design will instantiate a IBUFDS_GTE* and they will try to loc to the same site.  This will cause errors.  You must remove the IBUFDS_GTE* from one of the designs and drive its outputs from the buffer in the other design.  It is not clear whether you have the same problem with the GT*_COMMON but that is a possibility as well.  It would require the same solution.




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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: GTH Transceiver Wizard CPLL problem

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hi @tobis 

 

I think you can open the Implemented design and check the routings of refclk as well as the pin number

 

Thanks,

Boris

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Participant
Participant
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Registered: ‎02-23-2018

Re: GTH Transceiver Wizard CPLL problem

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@roym 

the 2 transceiver wizards generate a lot of files (see picture for the file output of 1 wizard).

its not clear to me which one i have to remove/ modify or connect with the other one. Maybe you can clarify, thanks

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Participant
Participant
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Registered: ‎02-23-2018

Re: GTH Transceiver Wizard CPLL problem

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@roym 

Another thing what makes me confused is that the simulation works without any errors. And i didnt have to modify any of the generated transceiver wizard files for that. 

 

@borisq 

both synthesis and implementation run without any errors or critical warnings. I already checked the implemented design, the refclk is as intended connected to both transceiver wizards. Also pin numbers are correct.

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Explorer
Explorer
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Registered: ‎03-16-2019

Re: GTH Transceiver Wizard CPLL problem

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IBUFDS is on the top module

gtwizard_ultrascale....example_top

 

find it bu tracking your gt refclk for example, mgtrefclk1_x0y9_p/n

 

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Participant
Participant
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Registered: ‎02-23-2018

Re: GTH Transceiver Wizard CPLL problem

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If the point you guys are trying to tell me is to connect the incoming reference clock to an IBUFDS_GTE4 and its output O then to the reference clock inputs of the 2 transceiver wizards (pin-name: gtrefclk0_in). I've already done that. That's not the issue. 

I also verified this in the Implemented design.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Re: GTH Transceiver Wizard CPLL problem

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hi @tobis 

 

can you put the two GTHs in a single GT Wizard IP?

 

if you toggle reset_all input port, can CPLL lock?

 

Thanks,

Boris

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Participant
Participant
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Registered: ‎02-23-2018

Re: GTH Transceiver Wizard CPLL problem

Jump to solution

I solved my problem. Apparently it was due to wrong reset behaviour. Additionally for GTH transceivers, make sure to use the calibration block if you intend to change line rates (Xilinx AR 70485). After caring about these things, i could get the CPLL of 2 separate transceiver wizards to work.

Thanks for all of your help!

View solution in original post