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Registered: ‎11-08-2018

GTH rx_cdrlok_out signal

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Hello,

I have a working VHDL code with GTH Tx to GTH Rx communication scenario with 1 HSSL at 10 Gbps.

My question is simple:

When I emulate a link loss at Rx level (GTH_RX_P=0 and GTH_RX_N=0) after let's say 100 us, the RX_CDRLOCK_OUT remains high (simulation is still running and so far at 3.146 ms, meaning almost 3 ms after ths link loss) so,

Is this signal dropping to 0 any time?

I am asking because I don't have an available board right now to test it and simulation lasts long (it is a whole FPGA design I have).

By the way,the GTH is configured for normal operation (CDRHOLD=0 and CDROVRDEN=0).

Thank you for your help

Regards,

 

 

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Moderator
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Registered: ‎07-30-2007

It is connected and generally works well on the first lock indication but it does not always or reliably detect when the signal is not locked.  It is very difficult to make a reliable signal for this that will work at all line rates, voltages, temperatures, with and without spread spectrum and never give a false indication or least it would be too expensive in terms or chip real estate.  And we don't want to create system resets when they are not needed.  




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Moderator
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Registered: ‎07-30-2007

The rxcdrlock signal is not normally used because of problems like this.  Normally data is tested to make sure the link is good.  This is a better test since it tests for all problems and not just CDR issues.  We normally look for no errors in an 8B10B signal and make sure a 64/66 signal has block lock.  If you have good data the CDR is locked well enough and if you don't have good data it doesn't matter if the cdr is locked.




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540 Views
Registered: ‎11-08-2018

Thank you, 

I am ok with the data based evaluation. I read that in some topics.

 

But does the rxcdrlock signal drops to 0 or not at some point?

 

Is it connected to something inside the gth transceiver?

 

Regards

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Moderator
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Registered: ‎07-30-2007

It is connected and generally works well on the first lock indication but it does not always or reliably detect when the signal is not locked.  It is very difficult to make a reliable signal for this that will work at all line rates, voltages, temperatures, with and without spread spectrum and never give a false indication or least it would be too expensive in terms or chip real estate.  And we don't want to create system resets when they are not needed.  




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Newbie
Newbie
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Registered: ‎07-30-2020

I'm now using KU115 device, I have a GTH project with 8 lane 2.97Gbps RX.When test on board, the rxcdrlock signal toggles every few microseconds.

My question is why the rxcdrlock signal toggle like this?i use Vivado Serial I/O Links to get the internal eye diagram, it has a good open eye diagram. 

 

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