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Visitor
Visitor
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Registered: ‎10-01-2019

GTH transceiver Rx Lane clocks not in sync. Lane0 goes out of sync with Lane1, 2, 3. Why does it happen?

Hi All,

I have the GTH connfigured and integrated into my design. The design has GTH from Xilinx and other parts which are RTL code written.

The GTH is configured to run at a line rate of 3 Gbps with four lanes in each channel. The set-up runs prefectly fine with Vivado standalone simulations and the test case passes. 

When I integrate this into my design, where it has the following:

1. SERDES is GTH serdes 

2. All the other layers are our custom code.

3. The GTH is configured to bypass Tx and Rx Buffer. Encoding decoding is done by our custom code

4. I see Tx FSM for all lanes are good

5. Rx FSM is good for Lane1, Lan2, Lane3 and all these 3 Rx clocks are in Sync

    Goes from IDLE, ALIGNED to LOCKED state and remains there

5a. Lane0 FSM is in goes from IDLE, ALIGNED to UNALIGNED and remains there

I see that the transition is due to the Rx0 Lane clock is out of sync with other Rx Lane clocks, Rx1, Rx2, Rx3 clocks

 

Please check the snapshot for further details. Can you please let me know under what conditions will this happen and why is the Rx Lane clocks not aligned with Lane0?

Regards

Hariharan K Srinivasan.

 

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4 Replies
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Visitor
Visitor
273 Views
Registered: ‎10-01-2019

Re: GTH transceiver Rx Lane clocks not in sync. Lane0 goes out of sync with Lane1, 2, 3. Why does it happen?

Please see the attachment.

Tool:Xcelium

 

Lane_clks_not_sync_Xilinx_Question_In_Forum.png
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Xilinx Employee
Xilinx Employee
194 Views
Registered: ‎03-30-2016

Re: GTH transceiver Rx Lane clocks not in sync. Lane0 goes out of sync with Lane1, 2, 3. Why does it happen?

Hello @harisrini 

 

This may happens, because rxoutclk_out is generated from RXOUTCLKPMA, which is recovered clock from input signal.
( To ensure please check RXOUTCLKSEL of your design )
Every lane is working independently, so you may see this kind of behavior. (rxoutclk is no synced)
Please_check_RXOUTCLKSEL.png

For multi-lane buffer bypass design, you need to use one RXOUTCLK from master lane and generate all lanes RXUSRCLK/RXUSRCLK2 from this clock.
Please see also UG576 Chapter4 for RX phase-alignment procedure.

>4. I see Tx FSM for all lanes are good
>5. Rx FSM is good for Lane1, Lan2, Lane3 and all these 3 Rx clocks are in Sync
> Goes from IDLE, ALIGNED to LOCKED state and remains there

Pardon me. What is the "TX FSM" ? Is it your custom code ?

Regards
Leo

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Visitor
Visitor
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Registered: ‎10-01-2019

Re: GTH transceiver Rx Lane clocks not in sync. Lane0 goes out of sync with Lane1, 2, 3. Why does it happen?

Hi Leo,

Thanks for the input and I will go through the UG to check how to do the Rx alignment.

Thanks once again for your reply.

 

Regards

Hariharan K Srinivasan.

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Xilinx Employee
Xilinx Employee
169 Views
Registered: ‎10-19-2011

Re: GTH transceiver Rx Lane clocks not in sync. Lane0 goes out of sync with Lane1, 2, 3. Why does it happen?

Hi @harisrini ,

to add to it, please also consider how you sample the data in the ILA. It looks like you are using a synchronous clock. The phase difference between rxoutclk0 to rxoutclk1-3 might not be as big as you see it.

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