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Contributor
Contributor
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Registered: ‎10-05-2018

GTWizard GTY example design for VCU118 not showing link status

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Hi,

I am trying to create a serial link using GTY transcievers connected to the FMC+ connector on the. I am using the GTWizard example design and I am not able to see a link status in  IBERT. if I provide any value to a DRP parameter, it is not stable, it keeps fluctuating from "User Value" to the value which I provide.

Capture.PNG

I am running the hb_gtwiz_reset_clk_freerun_in using an LVDS pair from the User_Si570_Clock_p/n on which is connected to bank 47 through pins H32 and G32 at a frequency of 250 MHz and my tranceiver reference clock is 125 MHz.The source of this clock is 104.9 and 104.10. I have used an IBUFDS and BUFG to use the differential clock.

Capture.PNG

 

I am trying to debug the cause of the link not being created. I have tried it for 28Gbps as well as 20Gbps.

My constraints are as follows:

UltraScale FPGAs Transceivers Wizard IP example design-level XDC file
# ----------------------------------------------------------------------------------------------------------------------

# Location constraints for differential reference clock buffers
# Note: the IP core-level XDC constrains the transceiver channel data pin locations
# ----------------------------------------------------------------------------------------------------------------------
set_property package_pin AN41 [get_ports mgtrefclk0_x0y1_n]
set_property package_pin AN40 [get_ports mgtrefclk0_x0y1_p]
set_property package_pin R41 [get_ports mgtrefclk0_x0y8_n]
set_property package_pin R40 [get_ports mgtrefclk0_x0y8_p]

# Location constraints for other example design top-level ports
# Note: uncomment the following set_property constraints and replace "<>" with appropriate pin locations for your board
# ----------------------------------------------------------------------------------------------------------------------
set_property package_pin H32 [get_ports hb_gtwiz_reset_clk_freerun_in_p]
set_property iostandard LVDS [get_ports hb_gtwiz_reset_clk_freerun_in_p]

set_property package_pin G32 [get_ports hb_gtwiz_reset_clk_freerun_in_n]
set_property iostandard LVDS [get_ports hb_gtwiz_reset_clk_freerun_in_n]

set_property package_pin AK14 [get_ports hb_gtwiz_reset_all_in]
set_property iostandard LVCMOS18 [get_ports hb_gtwiz_reset_all_in]

set_property package_pin AK13 [get_ports link_down_latched_reset_in]
set_property iostandard LVCMOS18 [get_ports link_down_latched_reset_in]

set_property package_pin AM12 [get_ports link_status_out]
set_property iostandard LVCMOS18 [get_ports link_status_out]

set_property package_pin AM13 [get_ports link_down_latched_out]
set_property iostandard LVCMOS18 [get_ports link_down_latched_out]

# Clock constraints for clocks provided as inputs to the core
# Note: the IP core-level XDC constrains clocks produced by the core, which drive user clocks via helper blocks
# ----------------------------------------------------------------------------------------------------------------------
create_clock -name clk_freerun -period 4.0 [get_ports hb_gtwiz_reset_clk_freerun_in_p]
create_clock -name clk_mgtrefclk0_x0y1_p -period 8.0 [get_ports mgtrefclk0_x0y1_p]
create_clock -name clk_mgtrefclk0_x0y8_p -period 8.0 [get_ports mgtrefclk0_x0y8_p]

# False path constraints
# ----------------------------------------------------------------------------------------------------------------------
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}]
##set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}]
set_false_path -to [get_pins -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]]
set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_meta*}]]
set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync1*}]]
set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync2*}]]
set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_sync3*}]]
set_false_path -to [get_pins -filter {REF_PIN_NAME=~*PRE} -of_objects [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_out*}]]


set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}]
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}]

 

Also, I'm not sure whether I am programming the on -board clocks correctly using the VCU118 SCUI. Do these clocks correspond to SI53340/U104.9 and SI53340/U104.10?:

Capture.PNG

I'd apprciate any help/advice/comments.

 

Thanks,

Naved

Capture.PNG
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Contributor
Contributor
532 Views
Registered: ‎10-05-2018

Hi jhua,

Thanks for your reply. The problem was that the input hb_gtwiz_reset_all_in was stuck to high as in the example design it is connected to a pin AK14 from the FMC connector instead of the FMC+ connector which I had been using.

Other than that, I did not know that In-System IBERT does not show the live BER and Errors like IBERT core. I was able to create eye scans after removing that reset.

Thanks,

alinave

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Xilinx Employee
Xilinx Employee
552 Views
Registered: ‎06-01-2017
The freerun clock and SCUI reading for Si570_1 (applies to your freerun clock) look fine.
What about the MGTREFCLKs which are sourced from FMC+. Is that valid on the board?
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Contributor
Contributor
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Registered: ‎10-05-2018

Hi jhua,

Thanks for your reply. The problem was that the input hb_gtwiz_reset_all_in was stuck to high as in the example design it is connected to a pin AK14 from the FMC connector instead of the FMC+ connector which I had been using.

Other than that, I did not know that In-System IBERT does not show the live BER and Errors like IBERT core. I was able to create eye scans after removing that reset.

Thanks,

alinave

View solution in original post

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