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Adventurer
Adventurer
1,371 Views
Registered: ‎02-06-2012

GTX TX buffer bypass and multiple channels

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Hello,

 

I have a system with multiple TX channels working with the same reference clock.

Hovewer, these TX channels are independent from data point of view. They are not "lanes" like in XAUI or PCIe.

Due to latency constraints (TX latency must be constant, or at least deterministic between system power cycles) I use the TX buffer bypass mode.

The general clocking structure is more or less the same as in this picture:

clocking_struct.png

Because each channel is independent I thought I could use the phase/delay alignment circuit in single auto mode to adjust phase between TXUSRCLK (XCLK) and PISO parallel clock.

From the datasheet description I understand that buffer bypass works by adjusting phase between

TXUSRCLK(XCLK) and PISO parallel clock inside the GTX channel.

However, when I look at the TXCLKOUT clock selection schematic I have some doubts.

 

tx_delay_aligner.png

This schematic suggests that it's not TXUSRCLK which is shifted, but it's TXOUTCLK (which is at the beginning of the clock distribution tree)

 This has a far reaching implications for my use case. It suggests that, even though my TX channels are independent, I still must configure GTX TX channels as multi-lane with master and slave channels.

 

Are my suspicions correct? How does this phase alignment circuit exactly work?

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Moderator
Moderator
1,750 Views
Registered: ‎07-30-2007

Re: GTX TX buffer bypass and multiple channels

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Only the channel that is the source of the TXOUTCLK can be the master channel so if you have the connection diagram configured the way you show you would have to use multi-lane with one master and the rest slaves.  To run independently and be their own master each channel would have to have its TXOUTCLK drive its own USERCLKs.  You might run out of clocking resources in a completely independent scheme.




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Moderator
Moderator
1,751 Views
Registered: ‎07-30-2007

Re: GTX TX buffer bypass and multiple channels

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Only the channel that is the source of the TXOUTCLK can be the master channel so if you have the connection diagram configured the way you show you would have to use multi-lane with one master and the rest slaves.  To run independently and be their own master each channel would have to have its TXOUTCLK drive its own USERCLKs.  You might run out of clocking resources in a completely independent scheme.




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Adventurer
Adventurer
1,294 Views
Registered: ‎02-06-2012

Re: GTX TX buffer bypass and multiple channels

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OK, thanks. That confirmed my suspicions.
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