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jiangzhk@126.com
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Registered: ‎06-07-2019

GTY running disparity error

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Hi, I'm using GTY in xcku3p device to receive 1G ethernet data. I created the GTY block using wizard and connected it up in my design, the data has 32bit interface, from what I see in chipscope, the rxctl1[3:0] randomly go high from time to time, which causes the rxbyterealign to be asserted.

I'm new to this and have no idea what might cause this problem.

 

running disparityrunning disparity

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roym
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Registered: ‎07-30-2007

Out of Table and disparity errors in an 8B10B are usually the result of bit errors caused by either poor signal integrity or under or over equalizing the input.  How long is your link and what equalization did you choose?  DFE would be the wrong choice and a wizard setting of auto with an Insertion Loss greater than 15 will end up with DFE.  If you are using LPM it can also overequalize on a very short link and there are settings we can recommend to turn it down if that is the case.




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roym
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Registered: ‎07-30-2007

Out of Table and disparity errors in an 8B10B are usually the result of bit errors caused by either poor signal integrity or under or over equalizing the input.  How long is your link and what equalization did you choose?  DFE would be the wrong choice and a wizard setting of auto with an Insertion Loss greater than 15 will end up with DFE.  If you are using LPM it can also overequalize on a very short link and there are settings we can recommend to turn it down if that is the case.




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jiangzhk@126.com
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Registered: ‎06-07-2019

gty_setting.PNG

Hi roym, thank you for your reply. It is a very short link and I'm using LPM, how should I set up these options properly in this case?


FYI. I did a measurement of how often the running disparity happens, there are around 18 disparity errors in around 6 seconds time. 

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roym
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Registered: ‎07-30-2007

I would say take a look at the GT power supplies and make sure everything is in the operating range and there is no noise there that might be the cause.  Also measure the jitter and quality of your reference clock and make sure there is nothing abnormal there.

It sound like this could be a link that is over equalizing.   The thing to do in this case is to turn off the equalizer as much as possible.  See UG578 on overriding the equalizer settings and set:

RXDFELPM_KL_CFG0, RXLPM_KH_CFG0 set to 0 and RX_OS_CFG1 is set to 10000000 (neutral)

It would be a good idea to take some Eye Scans with and without these settings.  Let me know if this helps.

 

 

 




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jiangzhk@126.com
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Registered: ‎06-07-2019

Hi roym,

I did not get to try out your equalizer settings as the device is on a remote site and they changed the cable from DAC to GBIC.

So when I was using DAC to receive data I see running disparity from time to time. But after they changed the cable to GBIC I don't see any running disparities. DAC is not really an IEEE standard so I think it caused signal integrity issue like you mentioned.

Thanks

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