07-03-2019 04:11 AM - edited 07-03-2019 04:15 AM
currently I try to simulate my generated GTY transceiver.
In the documentation the following picture is provided:
At first I do the GTTXRESET (using the 'gtwiz_reset_tx_pll_and_datapath_in') port.
After that I can see the TX RESET FSM is in state 'ST_RESET_ALL_TX_PLL_WAIT' ('sm_reset_all[2:0] = '011').
The QPLL0RESET is '1', too, after the 'ST_RESET_ALL_TX_PLL' state.
Now I would expect the GTPOWERGOOD goes high (over 50 ms simulation time) but it does not!
Obviously my PLL won't lock, because GTPOWERGOOD has to be high.
Here a snapshot of the TX RESET FSM in my simulation (time unit is in us; freerunning clock = 15 MHz):
Furthermore I've tried to reset the GTY using the 'gtwiz_reset_all_in' but without success. Again I'm stucking in state 'ST_RESET_ALL_TX_PLL_WAIT' with GTPOWERGOOD = 0 (over 50 ms simulation time).
Is there a further signal I have to drive for a GTPOWERGOOD indication?
Which issue in my reset control of the GT_WIZ - reset ports could cause this strange behaviour?
I'm using the Vivado 2018.3 version. Simulating with VCS-N-2017.12-SP2-4 (Full64) at Linux SuSe.
I've created all simulation libraries in Vivado for this specific VCS version.
07-03-2019 07:56 AM
Is it possible you are missing a reference clock to the GT or the freerunning clock input to the design? This is unusual in that you should be creating an example design that will deliver a working example design simulation. If you have done this simulation on your own you should be able to compare to the example design simulation.