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Visitor
Visitor
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Registered: ‎11-13-2018

Generating test pattern on ZynqMP GTR tranceiver

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Hi,

I'm working on a ZynqMP-based SoM, on an in-house board, and I'm trying to use the GTR tranceiver to act as USB3 device (5 Gbps). As my software works on reference boards and not on my own, I suspect signal integrity issues. Unfortunatelly when USB3 is failing, the USB stack falls back to USB2, making hard to measure Signal Integrity on GTR lines.

How can I set the GTR to continuously send any test packet that would allow me to check the quality of my physical link ? Debug registers are'nt documented in UG1087.

Thanks

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Moderator
Moderator
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Registered: ‎10-19-2011

A good way to see the signal integrity here would be IBERT for GTR. There is a tutorial in UG936 - Lab 10 on page 172 that will walk you through how to do this. You would then take a look at each eye to compair. It get an apples to apples comparison you may want to force the good board into USB2. I suspect this will still show a good/bad eye if signal integrity is your issue.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug936-vivado-tutorial-programming-debugging.pdf

The GTR are not like normal transcivers. Many of the tuning registers are not user accesible and not tunable like you would normaly find on our transcivers. Much of the tuning is handled by your protocol. 

Below is our GTR debugging guide. It will walk you through some other debug steps and dumps that might be valuable to debugging. 

For SI issues i start with the clocking. Check that your Clock meets the design requirements, and measure it on a scope, if you can, to see if its doing what you expect within its specs.

http://www.xilinx.com/support/answers/69483.htm

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1 Reply
Moderator
Moderator
458 Views
Registered: ‎10-19-2011

A good way to see the signal integrity here would be IBERT for GTR. There is a tutorial in UG936 - Lab 10 on page 172 that will walk you through how to do this. You would then take a look at each eye to compair. It get an apples to apples comparison you may want to force the good board into USB2. I suspect this will still show a good/bad eye if signal integrity is your issue.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug936-vivado-tutorial-programming-debugging.pdf

The GTR are not like normal transcivers. Many of the tuning registers are not user accesible and not tunable like you would normaly find on our transcivers. Much of the tuning is handled by your protocol. 

Below is our GTR debugging guide. It will walk you through some other debug steps and dumps that might be valuable to debugging. 

For SI issues i start with the clocking. Check that your Clock meets the design requirements, and measure it on a scope, if you can, to see if its doing what you expect within its specs.

http://www.xilinx.com/support/answers/69483.htm

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post