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Participant bitstreamer
Participant
671 Views
Registered: ‎08-15-2018

Hacking JESD Wizard Output

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Im looking to change a transceiver clock source, without having to bring in register write logic. I'm just testing the transceivers by themselves, so I'd like the bitstream to load in a configuration that isn't default.

 

If I change the following:

 

jesd_top_jesd204_phy_0_gt_gtwizard_top(
// other ports

.gtrefclk00_in(1'H0),
.gtrefclk01_in(1'H0),
.gtrefclk10_in(1'H0),
.gtrefclk11_in(1'H0),

 to:

 


.gtrefclk00_in(1'H0),
.gtrefclk01_in(1'H1),
.gtrefclk10_in(1'H0),
.gtrefclk11_in(1'H1),

 would this select REFCLK1 for both channels?

 

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
607 Views
Registered: ‎10-19-2011

Re: Hacking JESD Wizard Output

Jump to solution

Hi @bitstreamer,

 

you are right, there is no option for the refclk selection in the JESD wizard. So you have to set it as a location constraint in the toplevel xdc. Like this:

set_property package_pin AN36 [get_ports mgtrefclk1_x0y3_p]

Of course you have to adjust the name and location to your design.

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5 Replies
Xilinx Employee
Xilinx Employee
629 Views
Registered: ‎10-19-2011

Re: Hacking JESD Wizard Output

Jump to solution

Hi @bitstreamer,

 

these are the actual reference clock input pins. They were not used before. Putting a '1' on them does not bring a clock in.

Do you want to change the reference clock port dynamically?

Or do you want to generally use a different input?

On the last case, please regenerate the PHY core with the correct location selected, or just change the location constraint.

A dynamic change would be a different story.

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Participant bitstreamer
Participant
619 Views
Registered: ‎08-15-2018

Re: Hacking JESD Wizard Output

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Ah, I see. I'm looking to mux MGTREFCLK1 instead of MGTREFCLK0. I don't see that option in the IP wizard or in the debug ports.

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Xilinx Employee
Xilinx Employee
608 Views
Registered: ‎10-19-2011

Re: Hacking JESD Wizard Output

Jump to solution

Hi @bitstreamer,

 

you are right, there is no option for the refclk selection in the JESD wizard. So you have to set it as a location constraint in the toplevel xdc. Like this:

set_property package_pin AN36 [get_ports mgtrefclk1_x0y3_p]

Of course you have to adjust the name and location to your design.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Participant bitstreamer
Participant
335 Views
Registered: ‎08-15-2018

Re: Hacking JESD Wizard Output

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That doesn't really change the internal mux though. I'd assume there would be a quick way to edit HDL so the mux path could be altered if both clocks were assigned externally.

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Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎10-19-2011

Re: Hacking JESD Wizard Output

Jump to solution

Hi @bitstreamer,

if you want to have both refclks available for the core simultaneously, that would be a different story. Here you will need to change the transceiver setup to support two refclks. The IP is not supporting this directly. You will have to modify the transceiver code yourself.

If you want to have just one refclk the method of changing the location constraints should work.

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Don't forget to reply, give kudo and accept as solution
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