11-03-2018 06:26 PM
Im looking to change a transceiver clock source, without having to bring in register write logic. I'm just testing the transceivers by themselves, so I'd like the bitstream to load in a configuration that isn't default.
If I change the following:
// other ports
would this select REFCLK1 for both channels?
11-05-2018 09:01 AM
these are the actual reference clock input pins. They were not used before. Putting a '1' on them does not bring a clock in.
Do you want to change the reference clock port dynamically?
Or do you want to generally use a different input?
On the last case, please regenerate the PHY core with the correct location selected, or just change the location constraint.
A dynamic change would be a different story.
11-05-2018 08:48 PM
Ah, I see. I'm looking to mux MGTREFCLK1 instead of MGTREFCLK0. I don't see that option in the IP wizard or in the debug ports.
11-06-2018 03:58 AM
you are right, there is no option for the refclk selection in the JESD wizard. So you have to set it as a location constraint in the toplevel xdc. Like this:
set_property package_pin AN36 [get_ports mgtrefclk1_x0y3_p]
Of course you have to adjust the name and location to your design.
02-09-2019 07:11 AM
That doesn't really change the internal mux though. I'd assume there would be a quick way to edit HDL so the mux path could be altered if both clocks were assigned externally.