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Scholar
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Registered: ‎12-07-2018

Help with 64B/66B Aurora Example

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Hello, I using the ZCU-106 Eval Board and I generated the example for the 64B/66B Aurora IP. When I try to generate the BitStream I get the following error:

 

[DRC NSTD-1] Unspecified I/O Standard: 16 out of 22 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DATA_ERR_COUNT[0:7], CHANNEL_UP, HARD_ERR, INIT_CLK_N, INIT_CLK_P, LANE_UP, PMA_INIT, RESET, and SOFT_ERR.

Aurora_error.jpg

When I look at the I/O Ports I don't see any problems. The IO Ports are assigned an IO Standard.

 

I will upload TCL script so it can be regenerated.

 

Thank you

Joe

 

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Moderator
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Registered: ‎05-02-2017

Re: Help with 64B/66B Aurora Example

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hi @joe306 ,

 

Please kindly once refer the following link 

https://forums.xilinx.com/t5/7-Series-FPGAs/DRC-23-20-Rule-violation-NSTD-1-Unspecified-I-O-Standard/m-p/745026#M20227
https://forums.xilinx.com/t5/Design-Tools-Others/Bitgen-Error-NSTD-1-and-UCIO-1/m-p/666759#M8843
https://forums.xilinx.com/t5/Implementation/DRC-23-20-Rule-violation-NSTD-1-unspecified-I-O-standard/m-p/725941#M16272
https://forums.xilinx.com/t5/Vivado-TCL-Community/set-property-SEVERITY-Warning-get-drc-checks-NSTD-1-not-working/m-p/332883#M406.

 

I believe and assume you need change your option from default to corresponding voltage of that pin that might be LDVS.

 

 

 

Regards
Chandra sekhar
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Scholar
Scholar
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Registered: ‎12-07-2018

Re: Help with 64B/66B Aurora Example

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I think the problem I have is the IO pins are not mapped appropriately to the ZCU-106 board.

Joe

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Moderator
Moderator
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Registered: ‎05-02-2017

Re: Help with 64B/66B Aurora Example

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hi @joe306 ,

 

Please kindly once refer the following link 

https://forums.xilinx.com/t5/7-Series-FPGAs/DRC-23-20-Rule-violation-NSTD-1-Unspecified-I-O-Standard/m-p/745026#M20227
https://forums.xilinx.com/t5/Design-Tools-Others/Bitgen-Error-NSTD-1-and-UCIO-1/m-p/666759#M8843
https://forums.xilinx.com/t5/Implementation/DRC-23-20-Rule-violation-NSTD-1-unspecified-I-O-standard/m-p/725941#M16272
https://forums.xilinx.com/t5/Vivado-TCL-Community/set-property-SEVERITY-Warning-get-drc-checks-NSTD-1-not-working/m-p/332883#M406.

 

I believe and assume you need change your option from default to corresponding voltage of that pin that might be LDVS.

 

 

 

Regards
Chandra sekhar
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Scholar
Scholar
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Registered: ‎12-07-2018

Re: Help with 64B/66B Aurora Example

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Hello, I got things to work. I had to modify the xdc Constraints file and set the IO ports to board appropriate pins.

 

set_property LOC AH12 [get_ports INIT_CLK_P]
set_property LOC AJ12 [get_ports INIT_CLK_N]
# GPIO_SW_C
set_property LOC AL10 [get_ports RESET]
# GPIO_DIP_SW0
set_property LOC A17 [get_ports PMA_INIT]

# GPIO_LED_0_LS
set_property LOC AL11 [get_ports CHANNEL_UP]
# GPIO_LED_1_LS
set_property LOC AL13 [get_ports LANE_UP]
# GPIO_LED_2_LS
set_property LOC AK13 [get_ports HARD_ERR]
# GPIO_LED_4_LS
set_property LOC AM8 [get_ports SOFT_ERR]
# L6N_AD6N_64_N
set_property LOC K13 [get_ports DATA_ERR_COUNT[0]]
# L6P_AD6P_64_P
set_property LOC L14 [get_ports DATA_ERR_COUNT[1]]
# L5N_AD14N_64_N
set_property LOC J14 [get_ports DATA_ERR_COUNT[2]]
# L5P_AD14P_64_P
set_property LOC K14 [get_ports DATA_ERR_COUNT[3]]
# L4N_AD7N_64_N
set_property LOC J11 [get_ports DATA_ERR_COUNT[4]]
# L4P_AD7P_64_P
set_property LOC K12 [get_ports DATA_ERR_COUNT[5]]
# L3N_AD15N_64_N
set_property LOC L11 [get_ports DATA_ERR_COUNT[6]]
# L3P_AD15P_64_P
set_property LOC L12 [get_ports DATA_ERR_COUNT[7]]


##Note: User should add IOSTANDARD based upon the board
# Below IOSTANDARD's are place holders and need to be changed as per the device and board
set_property IOSTANDARD DIFF_SSTL12 [get_ports INIT_CLK_P]
set_property IOSTANDARD DIFF_SSTL12 [get_ports INIT_CLK_N]
set_property IOSTANDARD LVCMOS12 [get_ports RESET]
set_property IOSTANDARD LVCMOS18 [get_ports PMA_INIT]

set_property IOSTANDARD LVCMOS12 [get_ports CHANNEL_UP]
set_property IOSTANDARD LVCMOS12 [get_ports LANE_UP]
set_property IOSTANDARD LVCMOS12 [get_ports HARD_ERR]
set_property IOSTANDARD LVCMOS12 [get_ports SOFT_ERR]

set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[0]]
set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[1]]
set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[2]]
set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[3]]
set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[4]]
set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[5]]
set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[6]]
set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[7]]

 

Thank you,

Joe

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