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Observer eagerr
Observer
1,666 Views
Registered: ‎01-12-2016

How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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Problem:

I need to configure a GTX channel to be runtime configurable to support 10.0, 5.0, 2.5 and 1.25 Gbps operations.

 

Status:

I've successfully used the GT Wizard to create a GTX instantiation that allows me to switch from 5.0, 2.5 and 1.25 via the CPLL using the RX/TXRATE select signals.

I've successfully used the GT Wizard to create a GTX instantation that opeates at 10.0 Gps using the QPLL.

 

Question:

How do I use the GT Wizard to create a GTX instantitation that allows me to switch between the QPLL that is required for 10.0 Gps and the CPLL that is requred for the lower rates as stated as as requirement in UG476 page 54 and 61.

 

Thanks

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Observer eagerr
Observer
1,724 Views
Registered: ‎01-12-2016

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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@jhua wrote:

Do you have a list of attributes that changed between the 4 wizard designs you built (as part of step #2)?

There should be a few that specifically relates to setting the PLL speed and line rate. If you have the full list, I can look for the relevant ones for you.

 

Check out AR#56137. The tcl script "gt_Attributes.tcl" helps in dumping all GT COMMON and CHANNEL attributes to an output text file gtParams.txt. You can then use a text compare software to find out the attribute differences between your 4 designs. The tcl script should be run on an synthesized or implemented design dcp.


I do and  I will check out AR#56137.

Thanks for all of your help.

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Xilinx Employee
Xilinx Employee
1,640 Views
Registered: ‎06-01-2017

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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For dynamically changing line rates, we recommend the following guideline:

1. Generate GT wizard designs for every line rate

2. Find out all the COMMON and CHANNEL attributes that changes between line rates

3. Pick one line rate to use as the base line rate

4. During run time, use T/RXRATE ports and wait for T/RXRATEDONE (if CPLL), or follow the sequence in UG476 page 54 and 61 to change between CPLL and QPLL

5. Use DRP to overwrite attributes to that of the new line rate

6. Assert full GT reset

 

The GT ports as required in the PLL switching sequence can be exposed to the GT top level in the wizard. In Encoding and Clocking tab, enable the ports in the "Optional Ports" section.

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Observer eagerr
Observer
1,630 Views
Registered: ‎01-12-2016

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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Thanks for the instructions.

 

However I do have some status/questions on a these  steps:

 

1) Completed

 

2) I have identified which signals are added and deleted between the different configurations.  And this is the crux of my problem.  How do I instantiate the GT such that I have access to the all of the CPLL and QPLL signals that are only present in each instance?

For instance:

5G Configuration w/ CPLL has "cpllfbclkhost", "cplllock", and "cpllreset" exclusively.

10G configuration w/ QPLL has "qplllock" and "qpllrefclklost" exclusively.

At minimum I need both the lock signals and the cpllreset.

 

3) I will be choosing 10G as the baseline rate and using TX/RXRATE to select 10/5/2.5 and 1.25; with the caveat of transitioning from QPLL to CPLL when going from 10G to 5G.

 

4) UG476 states that I need to access RX/TXSYSCLKSEL to switch between CPLL and QPLL.  Unfortunately even though I selected those optional signals in my 10G instantiation, they do not show up in the entity-IO signal list.

 

5) Are there signals that only accessable via the DRP that can not be expressed via the GT Wizard?  If so which one do I need?

 

6) Will do.

 


@jhua wrote:

For dynamically changing line rates, we recommend the following guideline:

1. Generate GT wizard designs for every line rate

2. Find out all the COMMON and CHANNEL attributes that changes between line rates

3. Pick one line rate to use as the base line rate

4. During run time, use T/RXRATE ports and wait for T/RXRATEDONE (if CPLL), or follow the sequence in UG476 page 54 and 61 to change between CPLL and QPLL

5. Use DRP to overwrite attributes to that of the new line rate

6. Assert full GT reset

 

The GT ports as required in the PLL switching sequence can be exposed to the GT top level in the wizard. In Encoding and Clocking tab, enable the ports in the "Optional Ports" section.




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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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2) Exposing both CPLL and QPLL signals

I think you can do a trick by generating a new baseline wizard design where TX uses CPLL and RX uses QPLL. This way, the wizard top level will expose both CPLL and QPLL signals. This is not a intended use mode but will get you the signals you need.

 

4) TXSYSCLKSEL and RXSYSCLKSEL

Once you check those optional ports boxes in the wizard and regenerate output products, these ports should show up at the wizard xci top level (they are input ports to the gtwizard_0.v module). In your example design hierarchy, everything above the xci top level are in the RTL so you can modify them if these ports are not brought up to the hierarchy you intend to use them.

 

5) DRP access attributes. The DRP map can be found in Appendix D of UG476. Ports are not accessible by DRP so you control them through top level ports. The ports you need are the ones need to change between CPLL <-> QPLL.

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Observer eagerr
Observer
1,593 Views
Registered: ‎01-12-2016

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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2) So I used your trick to get the Wizard to expose the CPLL and QPLL signals at the same time and it worked.  However, I have now picked up two more signals that I don't know what to do with them:

GT0_TX_MMCM_LOCK_OUT

GT0_RX_MMCM_LOCK_OUT

 

Please advise how I should or should not use these new signals when I transition between CPLL and QPLL.

 

4) All of the GT IP I have been generating up to this point is with the "Include Shared Logic in core" option.  Once I switched to "Include Shared Logic in example design" I was able to find the TXSYSCLKSEL and RXSYSCLKSEL signals.  Yeah!

 

5) Now that I have access to the TX/RXSYSCLKSEL and CPLL/QPLL signals, is there any point to accessing the DRP registers? 

 

Thanks

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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>> GT0_TX_MMCM_LOCK_OUT

>> GT0_RX_MMCM_LOCK_OUT

I am not sure where these ports are showing up. Are they in the example design? I am guessing your design uses MMCMs to drive TX/RXUSRCLKs? I think these ports are used to indicate that MMCM has locked and your USRCLKs are stable. They may be used for the TX/RXUSERRDY signals. I don't see them in my design so I can't confirm. Check to see if this aligns with your example design connections.

 

>> is there any point to accessing the DRP registers?

It depends if you found any "attributes" (during step #2) that needs to be adjusted when changing line rates. The attributes can only be changed through DRP dynamically during operation.

The DRP interface operation is described in pretty good details in UG476 "Dynamic Reconfiguration Port" section. You can also check out AR#53788.

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Observer eagerr
Observer
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Registered: ‎01-12-2016

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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@jhua wrote:

>> GT0_TX_MMCM_LOCK_OUT

>> GT0_RX_MMCM_LOCK_OUT

I am not sure where these ports are showing up. Are they in the example design? I am guessing your design uses MMCMs to drive TX/RXUSRCLKs? I think these ports are used to indicate that MMCM has locked and your USRCLKs are stable. They may be used for the TX/RXUSERRDY signals. I don't see them in my design so I can't confirm. Check to see if this aligns with your example design connections.

 


They are showing up in the MGT IP and are brought up to the top level of the example design.

No my code does not use MMCMs to drive the TX/RXUSRCLKs.  This is all happening within the GT Wizard's IP output.

@My best guess is that MMCMs are being instantiated to handle the fact that we are running the RX @ 5Gbps with the CPLL and TX @ 10Gbps with the QPLL.  Again this only happens when I used your trick to enable both the CPLL and QPLLs, using that Quad's REFCLK0 to drive both PLLs.

I've reproduced it by creating a simple 2018.2 project that targets an Zynq 7030 -2ffg part and then using the GT Wizard to generate "mgt_ip".  If you look in the VHDL's Entity declaration you will see the MMCM signals.  I've attached the mgt_ip.xci for your reference.

 

Hopefully you can see a way to get the QPLL and CPLL exposed while not inferring an MMCM.

Once that is accomplished then I think I have everything I need to support multi-rate control of the MGT.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-01-2017

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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Do you intend to use TXOUTCLK as the source for RXUSRCLK/RXUSRCLK2?

The attached xci uses TXOUTCLK to source both TX/RXUSRCLKs, and because TX and RX runs at different rates, the wizard example design instantiates MMCM so that 2 different clock frequencies can be generated from the same TXOUTCLK source.

If you change the source of RXUSRCLKs to RXOUTCLK, then the MMCM is eliminated.

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Observer eagerr
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Registered: ‎01-12-2016

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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@jhua wrote:

Do you intend to use TXOUTCLK as the source for RXUSRCLK/RXUSRCLK2?

The attached xci uses TXOUTCLK to source both TX/RXUSRCLKs, and because TX and RX runs at different rates, the wizard example design instantiates MMCM so that 2 different clock frequencies can be generated from the same TXOUTCLK source.

If you change the source of RXUSRCLKs to RXOUTCLK, then the MMCM is eliminated.


Your answer makes sense.  However,  I realize now that this dual clock MGT approach will cause a problem during implementation.  This is because RXOUTCLK was not be routed to support 250MHz.  So how do I get around this problem?

 

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Xilinx Employee
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Registered: ‎06-01-2017

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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Once you have the QPLL/CPLL ports exposed, you can change the attributes using set_property. That should change line rate to 10G for the RX and RXOUTCLK should run at 250MHz. When you run implementation, the design should have RXOUTCLK timed to 250MHz.

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Observer eagerr
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Registered: ‎01-12-2016

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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@jhua wrote:

Once you have the QPLL/CPLL ports exposed, you can change the attributes using set_property. That should change line rate to 10G for the RX and RXOUTCLK should run at 250MHz. When you run implementation, the design should have RXOUTCLK timed to 250MHz.


Great! - And what "set_property" parameter do I need to override via my project's constraints file to change the RX's line rate?

I have looked through PG168 and could not find a "set_property" parameter that would enable me to set the RX line rate.

 

 

 

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Xilinx Employee
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Registered: ‎06-01-2017

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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Do you have a list of attributes that changed between the 4 wizard designs you built (as part of step #2)?

There should be a few that specifically relates to setting the PLL speed and line rate. If you have the full list, I can look for the relevant ones for you.

 

Check out AR#56137. The tcl script "gt_Attributes.tcl" helps in dumping all GT COMMON and CHANNEL attributes to an output text file gtParams.txt. You can then use a text compare software to find out the attribute differences between your 4 designs. The tcl script should be run on an synthesized or implemented design dcp.

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Don’t forget to reply, kudo, and accept as solution.
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Observer eagerr
Observer
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Registered: ‎01-12-2016

Re: How to configure a GTX to support 10.0, 5.0, 2.5 and 1.25 Gbps?

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@jhua wrote:

Do you have a list of attributes that changed between the 4 wizard designs you built (as part of step #2)?

There should be a few that specifically relates to setting the PLL speed and line rate. If you have the full list, I can look for the relevant ones for you.

 

Check out AR#56137. The tcl script "gt_Attributes.tcl" helps in dumping all GT COMMON and CHANNEL attributes to an output text file gtParams.txt. You can then use a text compare software to find out the attribute differences between your 4 designs. The tcl script should be run on an synthesized or implemented design dcp.


I do and  I will check out AR#56137.

Thanks for all of your help.

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