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Observer mrpetep1
Observer
935 Views
Registered: ‎03-13-2018

How to connect iBERT reference clock

xc7z045ffg900-2, Vivad0 2018.1_AR70325

 

(need to do similar with xc7vx690tffg1761-2)

 

Instantiate iBERT from IP catalog.

 

iBERT1.jpg

 

iBERT2.jpg

 

 

iBERT3.jpg

 

iBERT4.jpg

 

The ports are:

  TXN_O,
  TXP_O,
  RXOUTCLK_O,
  RXN_I,
  RXP_I,
  GTREFCLK0_I,
  GTREFCLK1_I,
  SYSCLK_I

 

I put a clk_wiz_0 between differential sysclk inputs and the single ended iBERT port. Why does the iBERT have a single-ended SYSCLK_I port when the GUI says the system clock source is differential on pins H9 and G9?

 

set_property PACKAGE_PIN H9 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
set_property PACKAGE_PIN G9 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS [get_ports SYSCLK_N]

 

 

(the xc7vx690tffg1761-2 will not have a separate sysclk input)

 

I tried to use MGTREFCLK1 111 pins for the 125 MHz reference clock input.

set_property PACKAGE_PIN W8 [get_ports refclk1_p]
set_property PACKAGE_PIN W7 [get_ports refclk1_n]

 

I tried using an IBUFDS between the differential clock input pins and the single-ended iBERT GTREFCLK1_I input (MGTREFCLK1 111 is selected in the GUI). I tried connecting refclk1_n to the single-ended iBERT GTREFCLK1_I input. I tried an MMCM and tried a CPLL. I tried leaving it open. It always results in an error.

 

Why are there two inputs when MGTREFCLK1 111 is selected in the GUI? Why is it single ended?

 

using an IBUFDS between the differential clock input pins and the single-ended iBERT GTREFCLK1_I input

IBUFDS_inst : IBUFDS
   generic map (
      DQS_BIAS => "FALSE"  -- (FALSE, TRUE)
   )
   port map (
      O => GTREFCLK1_I(0),   -- 1-bit output: Buffer output
      I => gt_refclk1_p,   -- 1-bit input: Diff_p buffer input (connect directly to top-level port)
      IB => gt_refclk1_n  -- 1-bit input: Diff_n buffer input (connect directly to top-level port)
   );

 

 

results in this error:

 

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance IBUFDS_inst at W8 (IPAD_X1Y70) since it belongs to a shape containing instance gt_refclk1_n. The shape requires relative placement between IBUFDS_inst and gt_refclk1_n that can not be honoured because it would result in an invalid location for gt_refclk1_n. ["C:/XP/Dqa/iBERT-dev0/iBERT-dev0.srcs/constrs_1/new/iBERT-dev0.xdc":8]

 

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance IBUFDS_inst at W8 (IPAD_X1Y70) since it belongs to a shape containing instance gt_refclk1_n. The shape requires relative placement between IBUFDS_inst and gt_refclk1_n that can not be honoured because it would result in an invalid location for gt_refclk1_n. ["C:/XP/Dqa/iBERT-dev0/iBERT-dev0.srcs/constrs_1/new/iBERT-dev0.xdc":9]

 

Aren't W8 and W7 MGTREFCLK1 111 inputs P/N?

 

I can't find an answer in Integrated Bit Error Ratio Tester 7 Series GTX Transceivers v3.0 LogiCORE IP Product Guide PG132 June 8, 2016 or 7 Series FPGAs GTX/GTH Transceivers User Guide UG476 (v1.12) December 19, 2016

 

I'm doing something wrong. How should the clocks be connected?

 

Thanks,

mrpetep1

 

 

 

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5 Replies
Observer mrpetep1
Observer
912 Views
Registered: ‎03-13-2018

In addition: How to connect iBERT reference clock

# also get this error: ERROR: [DRC NSTD-1] Unspecified I/O Standard: 2 out of 9 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: gt_refclk1_n, and gt_refclk1_p.


# OK, add this:

 

set_property IOSTANDARD LVDS [get_ports gt_refclk1_p]
set_property IOSTANDARD LVDS [get_ports gt_refclk1_p]


# result:

 

# [Vivado 12-1815] Setting property 'IOSTANDARD' is not allowed for GT terminals. ["C:/XP/Dqa/iBERT-dev0/iBERT-dev0.srcs/constrs_1/new/iBERT-dev0.xdc":11]


# [Vivado 12-1815] Setting property 'IOSTANDARD' is not allowed for GT terminals. ["C:/XP/Dqa/iBERT-dev0/iBERT-dev0.srcs/constrs_1/new/iBERT-dev0.xdc":12]

 

Either way it fails and reports an error.

 

Please advise!

 

Thanks,

mrpetep1

 

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Moderator
Moderator
905 Views
Registered: ‎07-30-2007

Re: In addition: How to connect iBERT reference clock

The reference clock is a specialized port that only takes a differential input.  Do not specify the IO standard.  It is understood.  You specify the IO standard for the system clock and its pins in the wizard.  Create the example design from that and you should not need to edit the input buffers IO standards or pins at all.

Roy


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Observer mrpetep1
Observer
897 Views
Registered: ‎03-13-2018

Re: In addition: How to connect iBERT reference clock

Thanks for the reply.

 

I understand that the reference clock is a differential input. The iBERT has two single-ended inputs even though I specified the clock input to use.

 

How is the differential reference clock input supposed to be connected to the single-ended iBERT input? Everything I tried resulted in an error.

 

"The example design"? Why would I create an example design?

 

 

 

Thanks,

mrpetep1

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Moderator
Moderator
891 Views
Registered: ‎07-30-2007

Re: In addition: How to connect iBERT reference clock

The example design is what is going to set up all of the input buffers and constraints that you are struggling with.  If you right click on the instantiation and choose open example design the example design will be created.  In the case of the IBERT it IS the ibert design.  From there you only have to implement a bitstream and load it into the device.  

 

If your system clock is not the frequency you want I would suggest switching from the external system clock to the internal one which will send the reference clock into the fabric and let it be the system clock as well.

Roy


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Observer mrpetep1
Observer
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Registered: ‎03-13-2018

Re: In addition: How to connect iBERT reference clock

Roym,

OK thanks, I knew there would be an 'ah-ha'. I tried making an example project with the xc7z045ffg900-2 and it'll be good for now.

 

IBERT for 7 Series GTX Transceivers v3.0 18 PG132 June 8, 2016 has an "example design" chapter but I didn't get the impression from the "Designing with the Core" or "Design Flow Steps" chapter that I had to create an example design.

 

I assume I can use the "example design" as a component so I can add some logic to generate a reference clock, is that correct? (I haven't tried that yet).

 

Thanks,

mrpetep1

 

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