cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
borial
Observer
Observer
7,881 Views
Registered: ‎05-14-2013

How to get the GTX Quad's pin location of ZYNQ devices

We can get the location information of Integrated PCIe of Kintex or Vertex in UG476: 7 Series FPGAs GTX/GTH Transceivers User Guide. But there is no information about ZYNQ devices.

Where to find the location information about ZYNQ devices? How to associat the Pin Number with GTX Quad?

I generated a PCIe core of ZYNQ 7045, here is the ucf constrains:

 

 

INST "refclk_ibuf" LOC = IBUFDS_GTE2_X0Y7;
 
#
# Transceiver instance placement. This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs. Please refer to the
# Virtex-7 GT Transceiver User Guide (UG) for more information.
#
# PCIe Lane 0
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y15;
# PCIe Lane 1
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y14;
# PCIe Lane 2
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y13;
# PCIe Lane 3
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y12;
# PCIe Lane 4
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y11;
# PCIe Lane 5
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y10;
# PCIe Lane 6
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y9;
# PCIe Lane 7
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y8;

 

0 Kudos
7 Replies
beckman
Visitor
Visitor
7,430 Views
Registered: ‎12-04-2013

Did you get an answer?  I have the same issue.

 

 

0 Kudos
yenigal
Xilinx Employee
Xilinx Employee
7,423 Views
Registered: ‎02-06-2013

Hi

 

Have a look at the below document where you can get the pin location information about the GTX.

 

http://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
beckman
Visitor
Visitor
7,414 Views
Registered: ‎12-04-2013

Satish:

 

Thanks for your reply.  I must be missing something.  If I have a constraint like this:

 

# PCIe Lane 0
INST "pcie_7x_v1_9_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y15;
 
I can see that PCIe Lane 0 is using GTXE2_CHANNEL_X0Y15.  ug865 lists the pins for the transceivers but refers to them by type, i.e. MGTXRXN3_110.  There is no correlation between what pins does transceiver GTXE2_CHANNEL_X0Y15 use.  
 
ug476 does have this information.  If you look at page 343 you can see how the transceiver maps to the pins for the FFG900 package but this is for Virtex-7 devices.  I'm looking for the same information for the Zynq device in this package.
 
I suppose if I built up an FPGA project in Vivado, the tool would tell me but I'm just working on a schematic right now.
 
Any ideas?
 
Thanks,
0 Kudos
bethe
Xilinx Employee
Xilinx Employee
7,374 Views
Registered: ‎12-10-2013

In Vivado there are 3 ways to determine the pinout of the PCIe core for Zynq:

 

If you open up the synthesized design - package, you can zoom into the MGT IO PAD areas - and look for pci_exp_txp or _txn or _rxn corresponding to your PCIe lanes (i.e. pci_exp_txp[0]) will show you the pin location. 

 

You can also do this by opening the implemented Device view, searching for the GTXE2_CHANNEL_X0Y15 (for example - based on your constraints), and then zoming in to the IPADs and OPADs.

 

Finally, the package pins tab will also relate the Pin name with the pci_exp_txp[0], etc. and the Site Type name (MGTXTXP1-112, for example), the IOB alias (OPAD_X0Y27, for example).  You will just need to expand the IO Banks to find these. 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
marksb
Visitor
Visitor
4,300 Views
Registered: ‎02-13-2016

3 years later and still no answer of where to find the documentation on the GTX locations vs the GTX wizard designations.  The answers given only work if you actually have a design that will synthesize.  You should be able to determine beforehand what the correct assignments will be instead of making guess (which take 15-20 minutes) to see if this time it will work.

 

The direct questions for a Zynq 7045 in a ffg676 package are:

GTXwizard clock source says REFCLK0 Q2, which package pins is it?

GTXwizard clock source says REFCLK1 Q2, which package pins is it?

GTXwizard clock source says REFCLK0 Q3, which package pins is it?

GTXwizard clock source says REFCLK1 Q3, which package pins is it?

GTXwizard location GTX_X0Y8 (which is not defined in the documentation for this specific package), which package pins is it?

GTXwizard location GTX_X0Y9 (which is not defined in the documentation for this specific package), which package pins is it?

GTXwizard location GTX_X0Y10 (which is not defined in the documentation for this specific package), which package pins is it?

GTXwizard location GTX_X0Y11 (which is not defined in the documentation for this specific package), which package pins is it?

GTXwizard location GTX_X0Y12 (which is not defined in the documentation for this specific package), which package pins is it?

GTXwizard location GTX_X0Y13 (which is not defined in the documentation for this specific package), which package pins is it?

GTXwizard location GTX_X0Y14 (which is not defined in the documentation for this specific package), which package pins is it?

GTXwizard location GTX_X0Y15 (which is not defined in the documentation for this specific package), which package pins is it?

 

Nobody at Xilinx can answer this question?

 

0 Kudos
4,135 Views
Registered: ‎01-04-2017

Hello, Friend.

 

The information you seek is in the Zynq SoC Ref Manual.

0 Kudos
foxnboy
Observer
Observer
935 Views
Registered: ‎12-09-2016

i also have the same question

Tags (1)
0 Kudos