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jhegeman
Observer
Observer
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Registered: ‎09-26-2018

How to map UltraScale+ MGT X_Y naming to 127/228 numbering?

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Dear all,

 

Is there anyone who can help me understand the mapping between the X_Y-like naming of MGTs in UltraScale+ devices and the numbering that spans 119-133 (for GTYs)? I have tried to find this in the various user guides, but so far without luck. Or am I doing something wrong to think this information is useful?

 

Best regards,

Jeroen

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karnanl
Xilinx Employee
Xilinx Employee
545 Views
Registered: ‎03-30-2016

Hello @jhegeman 


One option is to check UG575 Chapter1.
https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf (Chapter 1)

For Example XCVU13P Bank diagram below :
-- Quad 135 channel0 is X0Y60, Quad 135 channel1 is X0Y61 ... and so on.
US+_GTY_QUADS.png


Note :
Using this diagram is very helpful, because you can also notice where the RCAL quad for your GTYs.

Thanks & regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
546 Views
Registered: ‎03-30-2016

Hello @jhegeman 


One option is to check UG575 Chapter1.
https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf (Chapter 1)

For Example XCVU13P Bank diagram below :
-- Quad 135 channel0 is X0Y60, Quad 135 channel1 is X0Y61 ... and so on.
US+_GTY_QUADS.png


Note :
Using this diagram is very helpful, because you can also notice where the RCAL quad for your GTYs.

Thanks & regards
Leo


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

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borisq
Xilinx Employee
Xilinx Employee
521 Views
Registered: ‎08-07-2007

hi @jhegeman 

 

In addition, GT Wizard GUI also can show you the mapping as below figure shows.

 

Thanks,

Boris

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mapping.png
jhegeman
Observer
Observer
509 Views
Registered: ‎09-26-2018

Hi @karnanl, @borisq,

 

Thanks! That shows that I should stop skipping to the pin-out section for my FPGA when looking at UG575!

 

Cheers,
Jeroen

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