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srdatucsd
Adventurer
Adventurer
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Registered: ‎09-06-2016

How to replicate ports created with IP and example design

My last attempt to get this answered 3 weeks ago got me more confused and wasted a ton of trial and error time.  Rather than ask for an explanation here, let me ask if there is a video or tutorial showing step by step how to do the following.

After creating four separately placed instances of an communication IP with the wizard, I want to place them under a top level design and implement.  If you have done this and have an example, I'd appreciate it.  I have received missing or conflicting written or out of date online advice, along with some incomprehensible verbal advice.  I'm new to this.  So I need to see all the steps rather than broad stroke statements.

1.  Do I add the .veo or the .xci or a whole directory or 4 directories to the top (?) or just cut and paste the instantiation templates into the top level .v ?  If directories, is it IP or example design directories?  If files, which files specifically?  If I need to cut and paste anything, what and where?

2.  Once the designs are pasted in, how can I tell which lines in the subdesigns represent I/O ports going to pins that I have to constrain if not so identified by comment?

3.  Equivalently, which signals are ports that I must declare differently in the top level for each port and name the same for each instance?

4.  Is there any difference doing this with a hard IP (eg cmac_usplus) vs a soft IP (eg aurora)?

Thanks in advance??

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yuko.2828
Adventurer
Adventurer
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Registered: ‎12-27-2018

Hi there,

 

1. I am assuming you are using RTL ( instead of BD ).
Just Instance top modules of all your IPs in the your top module.  It takes time but should be a very simple stuff.

All of your IPs should be generated inside the same Vivado project of your top module. 

If you generate all those four IPs in the Vivado , there is no need to add any of those files (xci or other ) since it added already.

Do not instance the Example Design of your IPs, directly to your top module. rather, you should study the Example Design carefully, and implement only the necessary part.

 

I do not understand number 2 and 3.

 

4. No different.

 

If you are new to these stuff, it would be better to ask someone in your workplace for a direction.
Perhaps It is more simple than you think.

 

Best regards.

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srdatucsd
Adventurer
Adventurer
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Registered: ‎09-06-2016

Thanks for the advice, but I'm still wiffled.

The word "Instance" is being used here as a verb.  For me that is precisely what needs explaining.  I'm confused to hear that I do not need to copy anything in from anywhere else because this advice disagrees with the IP user guide UG896 (p34-35) and FAE advice (add the example design).  To make matters worse, there seem to be two instantiation template for each IP in the case of CMAC in .veo files.  There is one for the module and one for GT's.  'Instantiate' one, both, or neither?

If there is more than one way to do things, it would be good to know that.  Right now I'd settle for one step-by-step example that works.

And yep, this is RTL.

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srdatucsd
Adventurer
Adventurer
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Registered: ‎09-06-2016

Here is another anomaly.

I created a top level skeleton, and I instantiated 4 ports underneath it.  But after I ran synthesis, one of the ports disappeared from the list in the hierarchy for sources and for sims.

 

This looks like a bug.  Is it?

Missing port 0.jpg
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roym
Moderator
Moderator
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Registered: ‎07-30-2007

Your top file has 4 instances of cmac_usplus_0.  I think you meant to increment the suffix on each instantiation.  That is why *_2/3/4 were not used.  You should be able to view the situation better if you click on the > and look further down in the hierarchy.  You will get a better view of what is going on. 




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srdatucsd
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Adventurer
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Registered: ‎09-06-2016

Thanks for catching that.  I think you are right, but I want to duplicate the problem to make sure it was my mistake.

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