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Visitor ada0007
Registered: ‎12-27-2017

How to resolve issue with different GTH in one Quad

Hi. I'm using Kintex UltraScale+ xcku9p.
I'm trying to create project with 4 x 1G GTH and 2 x 10G GTH. PCB has been routed as 3 x 1G GTH is in ONE Quad and 1 x 1G GTH and 2 x 10 G GTH in ANOTHER Quad. So I got this placement for each set of GTH.




But I get error message about unroutable placement of this configuration.
[Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets inst_chip/serdes_x4_1G_inst/serdes_x4_1g25_inst/inst/gen_gtwizard_gthe4_top.serdes_x4_1g25_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_common.gen_common_container[0].gen_enabled_common.gthe4_common_wrapper_inst/common_inst/qpll0outclk_out[0]] >

    inst_chip/serdes_x4_1G_inst/serdes_x4_1g25_inst/inst/gen_gtwizard_gthe4_top.serdes_x4_1g25_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_common.gen_common_container[0].gen_enabled_common.gthe4_common_wrapper_inst/common_inst/gthe4_common_gen.GTHE4_COMMON_PRIM_INST (GTHE4_COMMON.QPLL0OUTCLK) is provisionally placed by clockplacer on GTHE4_COMMON_X0Y2
     inst_chip/serdes_x4_1G_inst/serdes_x4_1g25_inst/inst/gen_gtwizard_gthe4_top.serdes_x4_1g25_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X0Y3 ....
Should I generate something separately or with shared resources? How the project structure should looks like to make it routable? I mean, Is it possible to use 1 COMMON for 2 different kinds of CHANNEL?

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Xilinx Employee
Xilinx Employee
Registered: ‎06-01-2017

Re: How to resolve issue with different GTH in one Quad

There seems to be 2 COMMON modules instantiated in the same quad and therefore Vivado gives errors.

To use both QPLL0 and QPLL1 in the same quad to support different line rates, you can follow this AR#65228:


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