09-29-2019 07:30 PM
i have designed a virtex7690tffg1927 board,the voltage and clock of mgt are fine.when i use ibert to test mgt114,the ibert and bit stream is loaded.but when i creat link for 4 lane mgt114,there is only X0Y19 i can see in the list. this x0y19 can not link and locked. is there any problem in fpga pin? when i use ibert test mgt115(use mgt 114 mgtclk),4 lane of mgt115 is up,everything seems normal.
Please help me~
09-30-2019 10:07 PM
at first, you should be sure that your code is working properly, testing by another FPGA from this category is so helpful.
if the code work on this board, check your board and reviewing board methodology which Xilinx released.(check checkpoints on that document)
12-26-2019 10:08 AM
hi @bit_zym ,
This migh be due im proper clocking aslo
01-02-2020 04:56 PM
If the expected lanes are not showing up in Vivado GUI, check if the IBERT IP is generated correctly. Are you using example design? Check if the system clock is configured correctly; check both the pin location and the clock frequency.
For bank 114, check if near-end PMA loopback works (which you can turn on in the Vivado hardware manager -> create link -> look for loopback column). If so, the problem is likely on the board side.