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vilashini
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Registered: ‎05-10-2019

IBERT test in ZCU102

Is there any documentation for IBERT test in ZCU102 board?

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20 Replies
Mohangadusu
Xilinx Employee
Xilinx Employee
687 Views
Registered: ‎03-26-2021

Dear Vilashini,

 

The following link will help you out in testing the IBERT in ZCU102.

https://www.xilinx.com/support/documentation/boards_and_kits/zcu102/2019_1/xtp430-zcu102-ibert-c-2019-1.pdf

Best regards,

MOHAN.

Saravana1
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Registered: ‎07-17-2021

I have followed the document till synthesis implementation. As per the document we should get tick mark after synthesis implementation. But for me it is running for more than 7-8 hours but still tick mark is not appearing. Will u help me?

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Saravana1
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Registered: ‎07-17-2021

Am using Vivado 2019.2 version. I need to test SFP IBERT. So i have used Quad 230. But it is showing No link which I have attached in the document

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kdeshwal
Xilinx Employee
Xilinx Employee
589 Views
Registered: ‎11-12-2019

Hi @Saravana1 ,

Are you observing any errors/warnings in Message window?
Check out the IBERT design, if it is working fine or not  -
https://www.xilinx.com/member/forms/download/design-license.html?cid=a94723e1-738a-4a03-a120-ca2c0c48f231&filename=rdf0379-zcu102-ibert-c-2019-1.zip

Thanks,
Kuldeep 

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Saravana1
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Registered: ‎07-17-2021

To test SFP IBERT in ZCU102 What should be the Clock settings, Protocol definition, etc..,?

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Saravana1
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Registered: ‎07-17-2021

  • [Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top [current_fileset]).

 

When i open IBERT project am getting the above error

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kdeshwal
Xilinx Employee
Xilinx Employee
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Registered: ‎11-12-2019

Hi @Saravana1 ,

Verify if the top module is correctly selected and there should not be any "non module files".

Thanks,
Kuldeep

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Saravana1
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Registered: ‎07-17-2021

In top module what should be?

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Saravana1
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Registered: ‎07-17-2021

Now, IBERT is opening without any errors. Do  i need to do generate bitstream or directly connect to the hardware manager?

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Saravana1
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Registered: ‎07-17-2021

Generating bitstream is taking too long time more than 5 hours am waiting for it

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Saravana1
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Registered: ‎07-17-2021

Can anyone send me the bitstream file?

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Saravana1
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Registered: ‎07-17-2021

Iam getting the link for all the four ports of SFP as in the figure attached but I have connected only one SFP port. Can anyone tell me why is that so?

Capture.PNG
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Saravana1
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Registered: ‎07-17-2021

I have connected one SFP. Link is not establishing in Far-end mode.

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Saravana1
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Registered: ‎07-17-2021

Can anyone tell why the link is establishing in the nearend and not in far-end mode?

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eschidl
Xilinx Employee
Xilinx Employee
225 Views
Registered: ‎10-19-2011

Hi @Saravana1 ,

In near end loopback you close the loop between the local TX and the local RX. And as IBERT is running locally as well it can decide if the link is up or not.

In far end loopback you close the loop between the far-end TX and the far-end RX, means the received data on the local RX are send out again on local TX. On the local side now you do not have any idea what is happening on the channel. This is controlled by the channel partner (far-end). A local IBERT could only show a link up if the far-end TX is sending the same kind of sequence that is selected locally in the GUI (the received data are passed into the local fabric as well). You would need an IBERT running on the far-end to decide if the link is up or not.

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Saravana1
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Registered: ‎07-17-2021

To make IBERT work in far end what would I do? I have connected SFP to on the board. SFP has two ports(Tx and Rx) and I have done loopback

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eschidl
Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @Saravana1 ,

when you do an external loopback with a SFP module you do not need to set any loopback in the IBERT GUI as you have already a loopback.

A setting of far-end loopback does not make any sense in this case.

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Saravana1
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Registered: ‎07-17-2021

Ok If I didn't set any loopback in the IBERT GUI also it is not working. Why is that so?. It is working only in near end

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eschidl
Xilinx Employee
Xilinx Employee
170 Views
Registered: ‎10-19-2011

Hi @Saravana1 ,

check if your SFP module is working. Some modules might need an enable bit set to work. A passive electrical loopback module should work.

If that is not it and near-end PMA loopback works fine, it could be the TX driver settings or the channel itself as this is the only things added. You will need to debug further why that is.

See if an eye scan shows anything like an eye or if it is completely closed.

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Saravana1
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Registered: ‎07-17-2021

Can we access Vivado GUI (BER ) through Python?

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