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Visitor lsbrg
Visitor
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Registered: ‎04-05-2017

IBERT testing problem, please help

I am working on a project with 2 FPGAs. There are 32 pairs of GTH between these 2 FPGAs. I uses a crystal oscillator (LV7745DV-156.25M) to generate source clock and pass to an ADCLK854 to generate 12 pairs reference clocks for these GTHs. Every 2 Quad share a reference clock (156.25MHz). These reference clocks connect to MGTREFCLK* through a pair of 0.01u capacitor. FPGAs has a stable system clock at 128MHz as well. I generated 2 IBERT core each with 4 Quads. Linerate was set at 10GMHz, reference clock reference was set at 156.25MHz, system clock was set to 128MHz. When I loaded the ibert core's example projects into FPGA1 and FPGA2, the FPGA2's IBERT core showed PLL locked, but FPGA1's showed not. The FPGA2's IBERT core passed the near-end PMA test, but not pass the near-end PCS test. I had generated Aurora 64B66B cores of 2 Quads for these FPGAs, and the Aurora core showed the FPGA1's PLL locked, and the link up and channel up were high.

Summary: I cannot understand following problems:
1, why FPGA1's ibert core shows PLL not locked but the Aurora core showed PLL locked?
2, why FPGA2's ibert core cannot pass the near-end PCS test, as it is tested inside the FPGAs, it should not be impacted by the fact outside the FPGA?

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