03-15-2019 06:33 AM
We have followed all the steps mentioned for generation of IBERT in UG908 Ch 14 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug908-vivado-programming-debugging.pdf). After generating bitstream and uploading on FPGA, it is not showing IBERT Core as stated in the document. We also restarted the host machine (FPGA didn't lose power i.e., soft reboot) but this problem still persist.
Please have a look asap.
One general and common thing we have noticed . Please dont mind some genuine feedback.Things like these should work out of the BOX. We spend a lot of time going through the manuals, we try so many times,but ultimately nothing works many a times and theres no help on internet as well. Please do have a look.
Thanks and Regards,
03-15-2019 02:07 PM - edited 03-15-2019 02:09 PM
In my experience this is always due to a missing clock - either choosing a bad pin or a clock that isn't present at startup like an R/TXOUTCLK, R/TXUSRCLK or the output of an MMCM. I would suggest using the reference clock as the system clock. Refclk0 on bank 230 would be especially good since the si570 should have 156.25 MHz present at power up.
On the IBERT clock settings tab for source choose the reference clock.
03-16-2019 03:24 AM
T11 is pin for the MGTREFCLK0P on Bank 230 i.e Silicon Labs Si53340 3.3V LVDS clock buffer.
USER_SI570_CLOCK0_P/N QSFP1 GTY230 REFCLK0 which is what you were refering to as per https://www.xilinx.com/support/packagefiles/usapackages/xcvu9pfsgd2104pkg.txt.
Additionally should I be selecting RXOUTCLK Probes? If so what must be settings for RXOUTCLK below.
Apologies a bit new into this , but on a tight deadline. Help is highly appreciated as its the need of the hour.
03-16-2019 04:36 AM
OK some good news. Sharing so that it may be of help in future.
I've got one step working i.e please see image below.
Please let me know if there's anything more to verify.
It has worked without selecting "Add RXOUTCLK Probes"
I'll follow next steps.
@roym thanks a lot. Please have a quick look and kindly keep replying back while I get it to work fully so that this thread can be of help in future to others.Your help and guidance is highly appreciated.
03-17-2019 10:25 PM
Anyone please guide me what next I must be doing. I was expecting Status to be 10Gbps on one of the links.
Setup is as below:
VCU1525 has 2 QSFP28 ports. One network port on FPGA has a Twinax Copper QSFP+ 40G cable which breaks out into 4 of 10 G each. One of the 10G is plugged into a LINUX host which has a 10G Solarflare. I was expecting atleast one below to show the link is up. NOt sure why it has not come up.
03-18-2019 02:44 AM
you can try near end pma loopback and see if it links.
check rx termination and make sure it is set to 800mV.
right click on the 'Name' row, and select RXUSRCLK/TXUSRCLK and check the frequency.
03-18-2019 03:17 AM
thanks @borisq Please note the below.
Thanks @borisq settings as expected i believe . RXUSERCLK and TXUSERCLK are 125 Mhz.
When the near end PMA is taken off Link Status says no link. As only one 10G connection is really connected i would have thought only one link to be up?
Please let me know if my understnding is wrong ?
03-18-2019 07:01 PM
yes, your understanding is correct.
in Near End PMA loopback mode, all RXUSRCLKs are 125.0xxx.
in Non loopback mode, all RXUSRCLKs are 125.1xxx except Link 2.
is Link #2 connected?
maybe the SFP cannot handle 10Gbps? if you slow down the line rate to 1Gbps, what happens?