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alex83uk
Adventurer
Adventurer
817 Views
Registered: ‎06-30-2016

Kintex Ultrascale+ 3G-SDI (GTY pins)

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Hi all,

I'm designing a pcb with a XCKU5P-1FFVB67, and I have 3 questions:

1) I have 4 pairs of 3G-SDI signals that I need to connect to the XCKU5P FPGA. Can I connect them to the bank 227?

2) Is the max clock rate 148.5MHz?

3) Should I connect my clock to MGTREFCLK0P_227 & MGTREFCLK0N_227; to MGTREFCLK1P_227 & MGTREFCLK1N_227; or it doesn't matter which pair?

Thanks in advance!

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karnanl
Xilinx Employee
Xilinx Employee
790 Views
Registered: ‎03-30-2016

Hello Alex @alex83uk 


> 1) I have 4 pairs of 3G-SDI signals that I need to connect to the XCKU5P FPGA. Can I connect them to the bank 227?

It should be okay.

SDI_Board_Implementation.png

> 2) Is the max clock rate 148.5MHz?

Please check PG289 and PG290 for more detailed information.
In our example design, we suggest to use 148.5 MHz for QPLL REFCLK.
Following Example design will give you a quick start for your design.

SDI_QPLL_CLOCK.png

 

>3) Should I connect my clock to MGTREFCLK0P_227 & MGTREFCLK0N_227; to MGTREFCLK1P_227 & MGTREFCLK1N_227; or it doesn't matter which pair?

It does not matter, since you can select the REFCLK pin location from UHD-SDI GT GUI.
SDI_REFCLK_selection.png


Hope this helps.

Regards,
Leo

 

View solution in original post

1 Reply
karnanl
Xilinx Employee
Xilinx Employee
791 Views
Registered: ‎03-30-2016

Hello Alex @alex83uk 


> 1) I have 4 pairs of 3G-SDI signals that I need to connect to the XCKU5P FPGA. Can I connect them to the bank 227?

It should be okay.

SDI_Board_Implementation.png

> 2) Is the max clock rate 148.5MHz?

Please check PG289 and PG290 for more detailed information.
In our example design, we suggest to use 148.5 MHz for QPLL REFCLK.
Following Example design will give you a quick start for your design.

SDI_QPLL_CLOCK.png

 

>3) Should I connect my clock to MGTREFCLK0P_227 & MGTREFCLK0N_227; to MGTREFCLK1P_227 & MGTREFCLK1N_227; or it doesn't matter which pair?

It does not matter, since you can select the REFCLK pin location from UHD-SDI GT GUI.
SDI_REFCLK_selection.png


Hope this helps.

Regards,
Leo

 

View solution in original post