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betontalpfa
Explorer
Explorer
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Registered: ‎10-12-2018

Linerate confusion using 7series (VC707) IBERT

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I want to scan the eye-diagram of my high speed link.

I tried to use IBERT example design on VC707 board. I have set linerate to 5Gbps

image.png

BUT when I test the design near-end-PMA-loopback mode (on my VC707 board) the link state shows 10Gbps:

image.png

Why?

I use:

  • Win 10
  • Vivado 2017.4
  • VC707 (xc7vx485tffg1761-2)
  • IBERT

 

 

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betontalpfa
Explorer
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Registered: ‎10-12-2018

I found the problem/solution.

Brief:

Do not modify the line-rate of an IBERT, If you need the change, generate a new example design too.

Reason:

The line-rate cannot be changed of an IBERT, because the constraint file wont updated for the new values. (I dont know if is it a bug or a feature.) So if you dont want to modify the PLL and clock constrains by hand in the *.xdc file open a new example design.

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eschidl
Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @betontalpfa ,

what is your system clock setup and what do you use actually on the board?

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betontalpfa
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Registered: ‎10-12-2018

I have regenerated the project from scratch. And now its working well.

Maybe you, @eschidl, have found the solution.

Here is the Clock Settings of the WRONG desing (These are the default settings)

image.png

 

Here is the Clock Settings of the GOOD design (I switched to use QUAD clock)

image.png

Does this system clock measure the actual line rate?

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eschidl
Xilinx Employee
Xilinx Employee
993 Views
Registered: ‎10-19-2011

Hi @betontalpfa ,

yes, the system clock is used for the measurement.

Good to hear that it is working with the refclk as system clock for you.

I would actually expect both setups to work.
The only thing to try with the SYSCLK pins as system clock would be to divide it down.
The 200MHz system clock is above the DRP limit. So a division is necessary internally.
If that is the problem, you could try to setup the IBERT core with the same pin locations but a frequency of 100MHz. Then in the example design toplevel put a clock divider by 2 between the sysclk pins and the clock input of the IBERT core.

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betontalpfa
Explorer
Explorer
965 Views
Registered: ‎10-12-2018

Hi @eschidl 

I have confused again.

I have set the linerate to 1Gbps (Now I using CPLL because of the slow linerate.)

image.png

Now I dont use external system clock. I use the GTREFCLK (of the same quad) as system clock, which is a 125MHz clock.

image.png

However, the result is confusing again. I have set (PMA or PCS) near-end loopback, and it shows 2.5Gbps:

image.png

I have attached the properties of the common block and the channel.

Why is this mismatch occure?

Can I trust in the MGTREFCLK's 125MHz?

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betontalpfa
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Explorer
941 Views
Registered: ‎10-12-2018

I found the problem/solution.

Brief:

Do not modify the line-rate of an IBERT, If you need the change, generate a new example design too.

Reason:

The line-rate cannot be changed of an IBERT, because the constraint file wont updated for the new values. (I dont know if is it a bug or a feature.) So if you dont want to modify the PLL and clock constrains by hand in the *.xdc file open a new example design.

View solution in original post

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Reply