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baparicio
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Registered: ‎11-08-2017

PCIe pin swapping

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Hello,

I have a design with kintex ultrascale xcku040, and I'm using PCIexpress core with 4 lanes. I'm going to place the device in a custom board, so I would need to do a pin swapping for the PCIe pins. I suppose it is possible to do that, because it is indicated in page 205 of PG156, but I cannot find the way to do that. User constraints do not work, and in the ip core constraints file (pcie3_ip_gt.xdc, and pcie3_ip-PCIE_X0Y0) I cannot see the way to do that. Can anybody help?

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @baparicio 

I am using PCIe Example Design for this test. I found no issue doing pin-swap.

Result:

PCIE_test_result_for_DrJohnS_.png

I attached XDC file for your reference.

Thanks & regards
Leo

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @baparicio 

1. If you want to change the GT quad assignment, please change it using GUI. This is the easiest method.

2. If you want to change individual lane between , it can be done by modifying XDC file.

Please find the transceiver pin assignment XDC:
( for example : {project_name}.srcs/sources_1/ip/pcie4_uscale_plus_0/ip_0/synth/pcie4_uscale_plus_0_gt.xdc )

The following constraint decide the transceiver pin assigmment.
# Channel primitive location constraint
set_property LOC GTYE4_CHANNEL_X1Y5 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[25].*gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST}]

Comment-out above constrain, and add manual pin assigment something like this:
set_property package_pin AT3 [get_ports gtyrxn_in[1]]
set_property package_pin AT4 [get_ports gtyrxp_in[1]]
set_property package_pin AT8 [get_ports gtytxn_out[1]]
set_property package_pin AT9 [get_ports gtytxp_out[1]]

3. If your Vivado implementation result is good (timing is met etc), your design should be okay.

Thanks & regards
Leo

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drjohnsmith
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Registered: ‎07-09-2009

If I rember,

   when you creat the PCIe IP core,

     you specify which quadrent you wnat it in,

          that dictates which pins the PCIe core uses.

 

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baparicio
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Registered: ‎11-08-2017

Thank you for your answer.

I'm using PCIe core sited in X0Y0. What I want to do is swap the lane order, this is, by default lane order is:

rx_0 --> AB2

rx1 --> AD2

rx2 --> AF2

rx3 --> AH2

and what I need is:

rx0 --> AH2

rx1--> AF2

rx2 --> AD2

rx3--> AB2.

I've edited the file {project_name}/ip/xdma_0_0/ip_0/source/xdma_0_0_pcie3_ip-PCIE_X0Y0.xdc but with no result; the correction is:

###############################################################################
#
# PCI Express Block placement. This constraint selects the PCI Express
# Block to be used.
#
###############################################################################
#set_property LOC PCIE_3_1_X0Y0 [get_cells pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst]
set_property package_pin AH2 [get_ports gthrxp_in[0]]
set_property package_pin AF2 [get_ports gthrxp_in[1]]
set_property package_pin AD2 [get_ports gthrxp_in[2]]
set_property package_pin AB2 [get_ports gthrxp_in[3]]

 

after the implementation the pins are in the default location. I've tried also to change the file  {project_name}/ip/xdma_0_0/ip_0/ip_0/synth/xdma_0_0_pcie3_ip_gt.xdc with the same results. What am I doing wrong?

drjohnsmith
Teacher
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1,122 Views
Registered: ‎07-09-2009

Im prepared to be proved wrong,

  as I have not done PCIe 4 lane,

 

I have done plenty of Ethernet that need 4 SerDes GTX, and the order of the pins on one block in the quadrant if fixed,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
karnanl
Xilinx Employee
Xilinx Employee
1,090 Views
Registered: ‎03-30-2016

Hello @drjohnsmith 

Thank you for contributing a lot on Xilinx Forum.

>Im prepared to be proved wrong,
>as I have not done PCIe 4 lane,


I believe you are wrong :-)
I don't have much time today, but I will generete example design and show you the result (perhaps) tomorrow.

Thanks
Leo

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karnanl
Xilinx Employee
Xilinx Employee
1,077 Views
Registered: ‎03-30-2016

Hello @baparicio 

I am using PCIe Example Design for this test. I found no issue doing pin-swap.

Result:

PCIE_test_result_for_DrJohnS_.png

I attached XDC file for your reference.

Thanks & regards
Leo

View solution in original post

karnanl
Xilinx Employee
Xilinx Employee
1,075 Views
Registered: ‎03-30-2016

XDC

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baparicio
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Registered: ‎11-08-2017

Thank you everyone for the answers. I think this must be the issue: I create a very simple project with a xdma core in it, and change the pcie_gt.xdc file. When synthesis generates the output products, my changes are overwritten. If I try to change the file after generating output products, the change has no effect, and the pin swapping is not done.

Is there any option to fix this? I'm using Vivado 2017.4

 

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karnanl
Xilinx Employee
Xilinx Employee
1,015 Views
Registered: ‎03-30-2016

Hello @baparicio 

Try to generate your PCIe IP with "Systhesis Option"=Global, not "Out-of context per IP".
If this does not help , please ask a question on this forum : https://forums.xilinx.com/t5/Design-Tools/ct-p/DESIGN

This is not Transceiver problems.


Thanks & regards
Leo

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baparicio
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Registered: ‎11-08-2017

Thank you!

I finally got it! After synthesis, I opened the synthesized design, and in the schematic view I manually changed the pin numbers. That worked. 

karnanl
Xilinx Employee
Xilinx Employee
1,003 Views
Registered: ‎03-30-2016

Great ! @baparicio 
Thanks for updating your status.

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