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binayak_shrestha
Adventurer
Adventurer
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Registered: ‎10-05-2015

PDN noise budgeting for GTX in Zynq-7000 SoC

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Hi,

I'm using  Zynq-7000 SoC (XC7Z045-2FFG). For MGTAVTT and MGTAVCC rails, total pk-pk noise at the pins shouldn't exceed 10 mVp-p. 

However, recommended operating condition gives margin of +/- 30 mV.

Does this mean that I can provide DC margin (IR drop and regulator DC tolerance) of 20 mV and AC margin of 10 mV? 

 

Regards,

Binayak.

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karnanl
Xilinx Employee
Xilinx Employee
369 Views
Registered: ‎03-30-2016

Hello @binayak_shrestha 

I believe your understanding is correct for both MGTAVTT and MGTAVCC rails.

Regards
Leo

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1 Reply
karnanl
Xilinx Employee
Xilinx Employee
370 Views
Registered: ‎03-30-2016

Hello @binayak_shrestha 

I believe your understanding is correct for both MGTAVTT and MGTAVCC rails.

Regards
Leo

View solution in original post