08-02-2020 09:17 PM
I'm using Zynq-7000 SoC (XC7Z045-2FFG). For MGTAVTT and MGTAVCC rails, total pk-pk noise at the pins shouldn't exceed 10 mVp-p.
However, recommended operating condition gives margin of +/- 30 mV.
Does this mean that I can provide DC margin (IR drop and regulator DC tolerance) of 20 mV and AC margin of 10 mV?