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ckteng
Visitor
Visitor
618 Views
Registered: ‎06-22-2019

Partially Routed Nets JESD204B and GTPE2

Hi, I am using the Xilinx JESD204B IP with an Artix-7 and I'm getting partially routed net errors. 

The IP has a port with common0_pll_lock_out, common0_pll_clk_out, and common0_pll_refclk_out. My Verilog has all three signal connecting to the top-level output port, with no user-added logic. I did auto-generate a wrapper.

Does anyone have a methodology for getting the nets routed? It maybe useful to know that these signals seem related to GTPE2.

Please let me know if you need more info. Thanks!

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eschidl
Xilinx Employee
Xilinx Employee
556 Views
Registered: ‎10-19-2011

Hi @ckteng ,

the signals you mention are meant to be connected to another GTP CHANNEL primitive, especially *_pll_clk_out and *_pll_refclk_out. They are output signals of the GTP COMMON primitive, containing the PLLs for the GTP. There is no routing for them  to an output of the package or into fabric. If you do not use them, please leave them open.

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borisq
Xilinx Employee
Xilinx Employee
531 Views
Registered: ‎08-07-2007

hi @ckteng 

 

please have a look at the clocking in Figure 2-4 of UG482 to understand the connection.

https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf

 

common0_pll_clk_out should be PLL0OUTCLK.

common0_pll_refclk_out should be PLL0OUTREFCLK.

 

If it still failed, please post the error messages.

 

Thanks,

Boris

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ckteng
Visitor
Visitor
522 Views
Registered: ‎06-22-2019

Thanks, I don't think I need those signals if I don't need them to talk to an external DAC. Will try your advice and report back.

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ckteng
Visitor
Visitor
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Registered: ‎06-22-2019

Thanks, will take a look!
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ckteng
Visitor
Visitor
478 Views
Registered: ‎06-22-2019

Disconnected the two wires from the pins and no more problems! Thanks!!!!!!!!!