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jiwani
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Registered: ‎03-20-2019

Questions about GTP refclk (XAPP1097)

My board is based on xc7a50tcsg325-2. Recently,I want to migrate XAPP1097(a demo of SDI passthrough) project to my platform.

But my board only has one referece clock which is 148.5Mhz.The document of XAPP1097 says The TX section of the GTP transceiver, however, requires two different reference frequencies to support all five SDI bit rates. This is because the transmitters, in general, can only transmit at an exact integer multiple of the supplied reference clock frequency. Therefore, most SDI applications provide two separate reference clocks to the GTP Quad.

Can I use only one reference clock for GTP(SDI) TX or use a pll clock instead?

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florentw
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Registered: ‎11-09-2015

HI @jiwani 

The xapp1097 is quite clear: the 2 reference clock are required if you want to support the 5 SDI bit rates. The explanation is given in the same section:

 

This is because the transmitters, in general, can only transmit at an exact integer multiple of the supplied reference clock frequency.

 

If you use only one 148.5MHz clock, you won't be able to transmit the fractionnal bit rates (i.e. /1.001). But you can still transmit 3 SDI bit rates:

• 270 Mb/s for SD-SDI
• 1.485 Gb/s for HD-SDI
• 2.97 Gb/s for 3G-SDI

There is no way you can support the 2 fractionnal bit rates (i.e. 1.485/1.001 Gb/s (~1.4835 Gb/s) for HD-SDI and 2.97/1.001 Gb/s (~2.967 Gb/s) for 3G-SDI)) without the other clock.

One solution would be to have a programmable clock on your PCB.

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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jiwani
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That is to say it's feasible,but it doesn't fully support all rates of SDI?
I migrate xapp1097 passthrough demo to my design(only used one reference clock).The rx module does work( I convert YCbCr in sdi to RGB and display with VGA),but the tx part seems to be always 0.I was very confused about this.
Thanks for your reply.
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florentw
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Registered: ‎11-09-2015

HI @jiwani 

 


That is to say it's feasible,but it doesn't fully support all rates of SDI?
[Florent] - Yes correct

I migrate xapp1097 passthrough demo to my design(only used one reference clock).The rx module does work( I convert YCbCr in sdi to RGB and display with VGA),but the tx part seems to be always 0.I was very confused about this.
[Florent] - What rate are you trying? Make sure it is not a fractionnal one. Do you see the txlock signal high?
Do you have the same VIO as in the xapp? Can you share a screenshot of the TX ios?
Thanks for your reply.

 


Florent
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sa_fpga
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Registered: ‎11-11-2019

Hello Jiwani,

I just read your post, that you converted YCbCr to RGB in your application. Did you use custom code for it or an IP? I'm currently trying to implemented a 3G-SDI to Full HD LVDS output. The LVDS output is working. I'm struggling now with the GTP part. Maybe you have an idea? https://forums.xilinx.com/t5/Xilinx-IP-Catalog/GTP/td-p/1047746

I read the XAPP1097, but due to missing VHDL wrappers I'm trying the combine the GT wizard with the SDI SMPTE IP. 

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jiwani
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微信图片_20191125220135.png

Here is my tx_vio

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florentw
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Registered: ‎11-09-2015

HI @jiwani 

What rate are you trying? Also where do you see that there are only 0s on the TX?


Florent
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jiwani
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I' m trying 3G-SDI 1920*1080@60P.I saw 0 by oscilloscope.

Another changes on my project is that the ports PLL1LOCKDETCLK_IN or PLL0LOCKDETCLK_IN  in module gtpe2_common should be 27Mhz and my board doesn't have a 27Mhz osillator.So I use a pll(50MHZ to 27Mhz) to generate a 27Mhz clock.Is that matter?

THANKS

 

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jiwani
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Hi sa_fpga!

I find all the code about xapp1097 here

Hope it can help you!

https://forums.xilinx.com/t5/Video/xapp1097/td-p/930500

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sa_fpga
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Registered: ‎11-11-2019

Hello Jiwani,

I got my GTP and SMPTE 3G-SDI Core running. The next step ist to extract the HSYNC, VSYNC & DATA_ENABLE signals from the 2x10bit wide SDI stream and convert the colorspace from YCbCr to RGB. Did you find also this part of the code in the XAPP1097? 

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florentw
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Registered: ‎11-09-2015

hi @jiwani 

I believe using a PLL to generate the 27MHz clock is fine. Even if you might want to confirm by testing the same on the xapp1097 design and see if it works


Florent
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jiwani
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I try my project on another board(based on xc7a75tfgg484 ).It seems  that all functions work very well(The codes are same).Maybe there are some problems with my old boards.Anyway,thanks for your help.

jiwani
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Registered: ‎03-20-2019

I can tell you my ideas about how to extract HSYNC,VSYNC &DATA_ENABLE signals.It's maybe not the best,but it still works.
Firstly,check our SDI IP core is the same one or not.The IP core in my project is called SMPTE SD/HD/3G-SDI.
There is a port called rx_ln_a.(My SDI source is not dual-link,so it only have rx_ln_a.)
rx_ln_a means the lines number of the SDI video stream data.

For example,if the SDI source transmit 1080p@60hz.
The rx_ln_a will increase from 1 to 1125 indicates one whole frame of a image.Then you can generate SYNC siganls by specific standards related with the line number.
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sa_fpga
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Hello Jiwani,

yes, I also use the same core.  Thanks for your ideas. This task seems not to be awfully difficult to realize but it still wonders me that there is no IP core which receives the ouput from SD/HD/3G-SDI and outputs RGB & HSYNC, VSYNC and D_ENABLE data. If somebody is avare such an IP please correct me!

Best Regards

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florentw
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Registered: ‎11-09-2015


@sa_fpga wrote:

Hello Jiwani,

yes, I also use the same core.  Thanks for your ideas. This task seems not to be awfully difficult to realize but it still wonders me that there is no IP core which receives the ouput from SD/HD/3G-SDI and outputs RGB & HSYNC, VSYNC and D_ENABLE data. If somebody is avare such an IP please correct me!

Best Regards


@sa_fpga 

Unfortunatly, this feature is only available in the UHD-SDI subsystem which are only available in Ultrascale+ devices. The UHD-SDI subsystem can have SDI, native video or AXI4-Stream output.

For older devices, you might want to check the SDI to video bridge. This not part of the IP catalog as not supported but this can help.

Regards

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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