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Observer
Observer
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Registered: ‎10-19-2018

SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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I have an encrypted IP CORE which implements Aurora8b10b in SFP+ channel, using 125MHz SGMII clock as mgt reference clock.

I need to implement an ethernet interface. Both are in the same quad (bank 113).

As the another mgt reference clock is an external SMA, I used the 114 bank reference clock which came from Si5324 Jitter Atenuator.

Both transceivers are working properly in different projects, but when I mixed them on same block diagram project, I get the following error:

Capture.PNG

 

If I understood correctly, each transceiver are instantiating a GTXE2_COMMON, which gives error because each quad has only one.

Searching in the forum I figured out that I need to implement one transceiver with Shared Logic in Core, the other with Shared Logic in Design in order to share the GTXE2_COMMON between the master GT and the slave GT. But I cannot do that because the SFP+ IP is encrypted. How to proceed in such case?

Any help will be appreciated. Thanks.

 

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi @dicler ,

creating another IP for the shared logic might not be necessary. You could do it this way:

  1. place the ethernet core in the BD in your project.
  2. configure it to your requirements and select shared logic in the example design
  3. right click on it in the BD and select generate example design
  4. add the needed modules of the shared logic out of the example design to your project; if necessary create a module with remaining logic or as toplevel for the shared logic and add this too.
  5. In your BD use "Add Module..." to insert the shared logic HDL in your BD directly. If you created a top module for it, it would just be one instantiation.
  6. connect it in the BD as in the example design.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hello @dicler 

I think this is a possible usecase.

>> each transceiver are instantiating a GTXE2_COMMON, which gives error because each quad has only one.

Your understanding is correct.


Unfortunately, does not matter if you are using CPLL or QPLL, Aurora 8B10B GUI will always generate IP with GTXE2_COMMON included inside the IP.

If you generate Aurora 8B10B IP with "Include Shared Logic in Example Design", your Aurora 8B10B IP will not have GTXE2_COMMON part inside the IP. Could you please try this configuration ?
You will need to address some input port correctly ( for ex. tied gt_qpllclk_quad and qpllrefclk_quad1 to fixed "0". Please see Example Design connectivity for details )
AURORA_8B10B_COMMON_IN_ExDes.png

Regards
Leo

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Observer
Observer
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Registered: ‎10-19-2018

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hello Leo

I cannot change Aurora8b10b component as it is inside an encrypted IP. I can just configure the ethernet interface, for which I am using AXI 1G/2.5G Ethernet Subsystem IP. But even if I generate this IP with "Include Shared Logic in Example Design" option, I am unable to tie the proper signals to the Aurora 8b10b master, as the encrypted IP does not have those signals in its interface.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi @dicler ,

you might give this thread a look:

https://forums.xilinx.com/t5/Serial-Transceivers/Re-Frequency-of-QPLL-clock-from-a-GTX-core/m-p/1072785#M6875

 

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Observer
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Registered: ‎10-19-2018

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Thank you, eschidl.

"If you have the shared logic in example design just comment out the GTXE2_COMMON instantiation. The synthesis will do the rest."

My design is in block diagram. How can I remove the GTXE2_COMMON in BD?
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi @dicler ,

you could grab the IP HDL sources and create your own custom IP with these, leaving out the COMMON there. You can then instantiate this in the BD. This would work both ways, shared logic in the core or example design.

When you put the shared logic in the example design, the ethernet IP core does not include the COMMON block. So you could keep it as IP. You would have to add the shared logic into your design, so you have access to the HDL there and can modify it. You could also put this then into a custom IP if you like.

 

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Observer
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Registered: ‎10-19-2018

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi, eschidl.


I am editing the HDL sources of AXI 1G/2.5G Ethernet Subsystem IP.
I found that GTXE2_COMMON is instantiated inside core_gt_common_i component.

gt_common.PNG

I commented gt_common_i instantiation in bd_42d4_pcs_pma_0_support.vhd file, which is located in

C:\...\project_name.srcs\sources_1\bd\VC707_EXAMPLE\ip\VC707_EXAMPLE_axi_ethernet_0_0\bd_0\ip\ip_2\synth

gt_common_2.PNG

My problem now is in creating the custom IP from the block design HDL sources. What is the recommended way for doing that?

I tried to create a new project, aiming to use Package New Ip from this project. I imported the HDL files into it, setted axi_ethernet_0_0.vhd as the top level and added every component below it. Now Vivado does not recognize some libraries related to IPs.

libs.PNG

I have found these libs in "C:\Xilinx\Vivado\2018.3\data\ip\xilinx". Should I add every lib needed as a new lib source? This is very time consuming, as every lib added requires new libs.

Thank you for your help.

 

 

 

 

 

 

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Observer
Observer
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Registered: ‎10-19-2018

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi @eschidl,

I forgot to add the XCI sources, so the Vivado was not recognizing the IPs.

My steps:

1. Created new project, adding axi_ethernet_0_0.vhd as Top Level.

2. Added bd_42d4.vhd and the XCI file of every IP inside ip.

3. For the PCS_PMA IP, from which the GTXE2_COMMON need to be removed by commenting its instantiation, I also added the HDL files that are inside 'synth' folder, in order to not re-generate output products.

IP hierarchy.PNG

4. Package the IP and load it in previous project. I am stucked here, because when I first synthetize the project, the output products are re-generated, what makes GTXE2_COMMON  instantiation back again. Any guidance into this?

Thanks

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Observer
Observer
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Registered: ‎10-19-2018

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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I found an AR which explains how to Modify an IP Subsystem in block diagram: AR57546 

I made another topic about it: https://forums.xilinx.com/t5/Xilinx-IP-Catalog/Modify-Subsystem-IP-in-Block-Diagram/m-p/1073994#M6439

Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi @dicler ,

why don't you generate the sgmii core with shared logic in example design? The common block instance is then in the part outside the core. And you can find the needed parts of the shared logic in the example design.

In your project you still have then the sgmii core from IP catalog. You could just put the logic from the example design into a verilog module, leaving out the common block instance. Then add all the files of this logic to the project and add the new verilog module directly to the BD with "Add Module ...".

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Observer
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Registered: ‎10-19-2018

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi @eschild,

Plase, confirm if I understood your sugestion correctly.

I should:

1. Create another project, select AXI 1G/2.5G Ethernet Subsystem IP in IP Catalog with 'shared logic in example design' option, and create the exemple project of it.

2. On the example project, create an IP comprising the sgmii core and the needed shared logic, leaving out the GTXE2_COMMON.

3. Instantiate this IP in the previous block design.

Thank you.

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi @dicler ,

creating another IP for the shared logic might not be necessary. You could do it this way:

  1. place the ethernet core in the BD in your project.
  2. configure it to your requirements and select shared logic in the example design
  3. right click on it in the BD and select generate example design
  4. add the needed modules of the shared logic out of the example design to your project; if necessary create a module with remaining logic or as toplevel for the shared logic and add this too.
  5. In your BD use "Add Module..." to insert the shared logic HDL in your BD directly. If you created a top module for it, it would just be one instantiation.
  6. connect it in the BD as in the example design.

 

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Observer
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Registered: ‎10-19-2018

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi, @eschidl 

I have done as you suggested, but I encapsulated the shared logic as an IP in order to have a differential clock interface input.

The sgmii core with 'Shared Logic in Example Design' expects to receive the inputs gt0_qplloutclk_in and gt0_qplloutrefclk_in from GT_COMMON, as shown in the next figure.

gt_floating.PNG

What I should do with these ports?

I think that since TXSYSCLKSEL and RXSYSCLKSEL in GT_CHANNEL instantiation are tied to ground (as explained in pg 38 and 41 of UG746), the datapath is sourced by CPLL, and so these qpll clocks have no effect at all.  I tried leave them floating and also tried connect them to some clock, what gives me this error message:

error.PNG

I have confirmed that both TXSYSCLKSEL and RXSYSCLKSEL are tied to ground:

sysclksel.PNG

Thank you for your support.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi @dicler ,

connecting them to ground should work.

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Observer
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Re: SGMII and SFP in same quad, sharing GTXE2_COMMON [VC 707]

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Hi, eschidl

It worked. Thank you for your support.

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