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Contributor
Contributor
322 Views
Registered: ‎11-25-2013

Sharing MGTREFCLK between two different PHYs in different quads and "[Place 30-143] Sub-optimal placement for an IBUFDS / GT component pair" warning

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I'm getting this warning in a design targeting the ZC706. I'm using the MGTREFCLK1 from Bank 110 which comes from the SI5324 chip to drive two distinct common blocks which themselves drive different PHYs. I've LOC'd the common blocks to GTXE2_COMMON_X0Y3 and GTXE2_COMMON_X0Y2 because the channels they serve are in those quads and the actual serial IO pins that I'm using are in those repective quads (Bank 111 and Bank 112).

With a simpler design, using only a 10GigE core in Bank 111 there is no problem. But perhaps I am missing something about sharing the REFCLK? The REFCLK drives an IBUFDS_GTE2 instance that I do NOT LOC- rather I only contrain the package pins for the differential REFCLK inputs. I leave the common clock select mux alone at 3'b001 and connect the output of the IBUFDS_GTE2 to the GTREFCLK0_IN of each common- trying to stay out of the way of the tool in routing the clock.

I'm operating under the understanding that the REFCLK can be used from up to two above or two below quads- so the REFCLK coming in to Bank 110 should be able to serve the quads in Bank 111 and 112 yes?

I can see in the device view that everything is placed where I expect it to be- is it safe to ignore this warning ( never feel good about that )?

Thanks

 

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Xilinx Employee
Xilinx Employee
312 Views
Registered: ‎10-19-2011

Re: Sharing MGTREFCLK between two different PHYs in different quads and "[Place 30-143] Sub-optimal placement for an IBUFDS / GT component pair" warning

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Hi @rsclancy ,

please have a look at ug476, page35 for the possibilities for the reference clock routing in 7 series transceivers:

"In general, the reference clock for a Quad (Q(n)) can also be sourced from the Quad below (Q(n–1)) via GTNORTHREFCLK or from the Quad above (Q(n+1)) via GTSOUTHREFCLK. For devices that support stacked silicon
interconnect (SSI) technology, the reference clock sharing via GTNORTHREFCLK and GTSOUTREFCLK ports is limited within its own super logic region (SLR)."

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3 Replies
Teacher xilinxacct
Teacher
314 Views
Registered: ‎10-23-2018

Re: Sharing MGTREFCLK between two different PHYs in different quads and "[Place 30-143] Sub-optimal placement for an IBUFDS / GT component pair" warning

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@rsclancy 

You may get some insights with the thread... https://forums.xilinx.com/t5/7-Series-FPGAs/placement-error-vivado-v2016-4-Place-30-143/m-p/759746#M21287

Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed. :-)

Xilinx Employee
Xilinx Employee
313 Views
Registered: ‎10-19-2011

Re: Sharing MGTREFCLK between two different PHYs in different quads and "[Place 30-143] Sub-optimal placement for an IBUFDS / GT component pair" warning

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Hi @rsclancy ,

please have a look at ug476, page35 for the possibilities for the reference clock routing in 7 series transceivers:

"In general, the reference clock for a Quad (Q(n)) can also be sourced from the Quad below (Q(n–1)) via GTNORTHREFCLK or from the Quad above (Q(n+1)) via GTSOUTHREFCLK. For devices that support stacked silicon
interconnect (SSI) technology, the reference clock sharing via GTNORTHREFCLK and GTSOUTREFCLK ports is limited within its own super logic region (SLR)."

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Don't forget to reply, give kudo and accept as solution
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Contributor
Contributor
302 Views
Registered: ‎11-25-2013

Re: Sharing MGTREFCLK between two different PHYs in different quads and "[Place 30-143] Sub-optimal placement for an IBUFDS / GT component pair" warning

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My bad, had the Ultrascale transceiver wizard bookmarked (576) which is where I read Q(n-2).... So straight 7 series only supports one above or below. Thanks.
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