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Participant
Participant
257 Views
Registered: ‎02-08-2019

Simulation with GTP IP core

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Hello 

I am new in GTP IP core generation and simulation.

I an created a RTL with GTP IP core on Artix Fpga for Vx1 application.

The genearted IP core with TX off  and only 8 lanes of RX in on. My component name is gtwizard_0.

When is right click on gtwizard_0 and open IP example design then example project is open in new window.

My question are

1. How do I know what this example is doing means what is its inuput and output?

2. How this example project is working.

 

Thanks

Manish

 

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Moderator
Moderator
217 Views
Registered: ‎07-30-2007

Re: Simulation with GTP IP core

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There are some instances where you don't have a design that will lend itself to making a loopback example design and the wizard won't create a good one for you.  In this case you don't have an output to feed to the input.  In some cases the wizard might create one for you but sometimes you will have to generate your own example design.  There are other cases too. If you don't have a means of doing comma alignment or block alignment in the design there won't be a functioning example design.




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Highlighted
Moderator
Moderator
218 Views
Registered: ‎07-30-2007

Re: Simulation with GTP IP core

Jump to solution

There are some instances where you don't have a design that will lend itself to making a loopback example design and the wizard won't create a good one for you.  In this case you don't have an output to feed to the input.  In some cases the wizard might create one for you but sometimes you will have to generate your own example design.  There are other cases too. If you don't have a means of doing comma alignment or block alignment in the design there won't be a functioning example design.




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Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------


View solution in original post