cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Participant
Participant
878 Views
Registered: ‎02-23-2018

Transceiver wizard 1.7, free run clock

Jump to solution

Hey guys,

based on an older 7 series design i try to implement a transceiver with dynamic line rate change for an Ultrascale+.

I understood that i have to use the calibration block if CPLL is used and line rate changing is desired.

In the old 7 series wizard, the free-run/DRP clock we used was 125MHz for supporting line rates from 1.25G up to 6.25G.

In the newer Transceiver wizard 1.7 for the Ultrascale+, the free-run/DRP clock is automatically limited depending on which line rate i put in. For instance the wizard limits the free-run clk to 78.125MHz if 3.125G is selected. 

Now i am confused which free-run/DRP clk frequency I have to choose if my transceiver should support line rate from 1,25G to 6,25G??? Or do i have to dynamically change this frequency depending on line rate?

 

Cheers!

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
856 Views
Registered: ‎10-19-2011

Hi @tobis,

please check with pg182, page 10/11, where this limitation is coming from. The dependency comes from the USRCLK2 used.
Just check with all line rate setups you want to use, what would result in the lowest frequency limit for the free running clock, and take this lowest frequency (or a lower one) as your free running clock for all setups. Then you would not need to change when stepping through your line rates.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
857 Views
Registered: ‎10-19-2011

Hi @tobis,

please check with pg182, page 10/11, where this limitation is coming from. The dependency comes from the USRCLK2 used.
Just check with all line rate setups you want to use, what would result in the lowest frequency limit for the free running clock, and take this lowest frequency (or a lower one) as your free running clock for all setups. Then you would not need to change when stepping through your line rates.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

Highlighted
Advisor
Advisor
846 Views
Registered: ‎12-03-2007

Hi @tobis ,

I've recently posted a related question [link]. The max speed of free-running DRP clock depends on the data width. I think you can choose the lower of two speeds.

 

Thanks,

Evgeni

Tags (2)