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Visitor
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Registered: ‎04-16-2019

Transceiver

I am working on a design where I have limited IO in the main system connector. I have 12 discrete signals that I would like to feed though an FPGA transceiver so I can bring out a diff pair of SerDes lines.  I need to run this for a distance of about 20 meters.

Is it usual for someone to use FPGA transceivers for signals outside of the FPGA fabric?

How can I exted the length of the cables to run these signals for 20m?

Where can I find serialization delay and deserialization delay information?? I would like to be able to calculate the delay from the time I insert the parallel signals in the FPGA until I get parallel out in the other end but I did not see much delay information in the documentations online (other than the one you can read from the FPGA).

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Adventurer
Adventurer
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Registered: ‎07-21-2015

You need to provide some more details. Are these twelve signals synchronous to the same internal clock? If so what is this clock frequency. Depending on this frequency it may be simpler to just load a 12 bit shift register and shift it out. More predictable too. Should easily work up to about 250 MHz, maybe even higher. If you want to get fancy you could use the serdes within the I/O pads. These are distinct from the hard transceivers built within the FPGA. And they should be able to drive 20m or so.  The downside is that you will also have to drive out a clock too. And synchronize the clock and data 'manually' on the receive end.

You could go the transceiver route but it's more work.

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Visitor
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Registered: ‎04-16-2019

@rmasand  the 12 signals are not synchronous to the same internal clock. They are slow signals (discrete logic high/low) that come from different parts in the system. I was under the impression that the SerDes and the Tranceivers in the FPGA were the same but from your answer looks like that is not true. To use the SerDes within the I/O pads, is that some specific I/O pins or all I/O can be configure to do this? What is the main difference between the SerDes within the IO pads and the transceivers?? Also what do you mean with synchronize the clock and data 'manually' on the receive end?  

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Teacher
Teacher
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Registered: ‎07-09-2009

How slow is slow signals ?

 

things like RS232 run great over long distance and carry 8 bits of informatoin,

   but at a M baud max ish.

 

 

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Visitor
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Registered: ‎04-16-2019

One requirement that I forgot to mention was that the delay from end to end should be less than 500 ns . Also the pulsewidth should be the same at each end.
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Teacher
Teacher
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Registered: ‎07-09-2009

What s the smallest pulse width u wish to transmit ? As it's going to be a sample your transmitting, the pulse at the receiver will not be the same size as at the transmitter .what variation can u get away with .

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Adventurer
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Registered: ‎07-21-2015

Yes @pgarci05  a transceiver (or a MGT in xilinx parlance), is distinct from a serdes (though it does incorporate one or more serdes). A transceiver is a hard macro within an FPGA capable of running at tens of Gb/s rates. Fairly complex block and not easy to use. (See UG476). The serdes with an I/O pad is a simple shift register capable of parallel-in serial-out operation and vice-versa. Much simpler to use. Due to it's simple nature it does require an external clock to be transmitted with the serial data, and the designer has to manage the timing for that clock. That's what I meant by 'manual'. And yes, all I/O pads within most modern devices, do include the SERDES. (See UG471 for example).
Hope that helps.

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Teacher
Teacher
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Registered: ‎07-09-2009

this thread might also be of interest,
https://forums.xilinx.com/t5/UltraScale-Architecture/high-speed-serial-I-O/m-p/964545#M9768
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Registered: ‎04-16-2019

@rmasand So I would have to run a Tx line, an Rx line and a CLK line from my source to the destination? Also what does clock managing entail?

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Adventurer
Adventurer
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Registered: ‎07-21-2015

That is correct @pgarci05 . You would have a differential pair in each direction and a differential clock. By 'managing' I mean you will have to account for the relative delays between the clock and data and adjust for them - probably using MMCM (clock managers) on the receive side to successfully capture the data.

 

Good Luck!

 

Ravi

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