US+ GTY RX Equalizer Disabling

[chsdkj]

In a US+ design here the electrical distance (PCB trace length) the 20Gbps signal needs to travel from the signal source to the GTY xcvr RX input pads is short (1").  For eye improvement it is desired to employ only deemphasis at the local TX source with no RX equalization used.

What means can be used to disable RX equalization (LPM and DFE, as discussed in UG578 (v1.3) on p.197-211)?

Is it possible to hold the RX equalization mechanism in reset to prevent it from functioning?

Is it possible to allow the RX equalization mechanism to function initially, but then freeze it from making further equalization changes afterwards?

For a lock-to-reference situation (RXCDRHOLD=1 and RXCDROVRDEN=0, per p.216), would RX equalization normally be functional?  If so, how would the equalization be accomplished (given, per Fig.4-12 and 4-13, that some sort of eye-diagram evaluation of the equalizer output needs to be performed, which would appear to be infeasible in a lock-to-reference situation)?

[roym]

The RX equalization is adaptive and usually LPM works well on a short channel.  It is not possible to turn equlization off but you can overide most LPM settings to 0 and get almost no equalization.  I would recommend checking the channels data eye with LPM engaged and see how big the eye is.  If it meets the eye mask minimums then it is gauranteed to work over PVT and that would be the best set up use because even if the unequalized Eye is bigger it wouldn't necessarily be guaranteed over PVT.  

It is possible to hold the LPM attributes at any point but similar to the discussion above that is not recommended.  See table 4-9 in UG578 for the *HOLD and *OVRDEN settings.

Equalization deals mainly with the amplitude of the incoming signal and is generally separate from the clock data recovery so it is functioning in lock to reference mode.

[chsdkj]

Roy,

Thanks for your prompt response!

When you say "overide most LPM settings to 0 and get almost no equalization", specifically which LPM settings do you have in mind?

Given that LPM (and DFE) is continually functioning and making equalization adjustments that affect the internal analog signal (that is then converted into a parallel digital word), how much jitter (effective change in the incoming serial signal edge timing) can be expected due solely to the equalization circuity as it makes modifications to the circuit parameters?

[roym]

RXDFELPM_KL_CFG0, RXLPM_KH_CFG0 set to 0.and RX_OS_CFG1 is set to 10000000.  When you override parameters they are fixed so there is no adaptation going on.  Keep in mind this is not recommended for a situation where the normal adaptation gives you a enough margin and only in very rare cases would normal adaptation fail on a short channel.

[chsdkj]

Roy,

Understood.

Presumably I could decide to keep the offset (OS) correction in force while suspending the LPM equalization, or vice versa, yes?

Note that there is no RX_OS_CFG1 attribute; perhaps you meant RXLPM_OS_CFG1 (cited in the description for RXLPMOSHOLD & RXLPMOSOVRDEN) or perhaps RXLPM_OS_CFG0?

[roym]

Yes, RXLPM_OS_CFG1.  You're free to pick and choose what you want to override and see what works best but nothing outside of the fully adaptive equalization is recommended.

[chsdkj]

Roy,

Understood.

Any ideas regarding my earlier equalization-change-related jitter-affect question?

[roym · Accepted solution]

I have nothing on any timing jitter that might be created.  That is something that we don't characterize.