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cbemlahe
Explorer
Explorer
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Registered: ‎09-18-2007

UltraScale Running MGT Tx/Rx at different rates (JESD204B)

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I have a purchased Xilinx JESD204B core and have used it with no problems for a transmit only design in Virtex-7.

I now need to design a transmit and receive design. Since the IP core GUI does not allow you to generate a simultaneous Rx and Tx core, I have made a Tx core and Rx core (both complete designs). Although this builds, it does not let you use the same MGT for Rx and Tx.

 

So I then made a JESD_PHY and a JESD_TX and JESD_RX core. Wiring them up is pretty Ok except when it comes to the clocking...

The MGT user guide says that the PHY TXOUT_CLK can be connected to the input TX_CORE_CLK (and same for RX clocks) but this fails place and route. I look at the example and I see that a IBUF_DS_GTE3 is used to take the REF clock through to the QPLLx clock. That bit is fine.

But I'm not understanding how to hook up the PHY: TX_CORE_CLK, RX_CORE_CLK, TXOUT_CLK, RXOUT_CLK  and the Tx and Rx IP Core's TX_CORE_CLK and RX_CORE_CLK.

 

I then looked at a self contained JESD core and I see that its used 3 primitives: BUFG_GT_SYNC, BUFG_GT and IBUFFD_GTE3. (so not what the user guide says). REFCLK is easy enough but the BUFG_GT seems to be a divide by 2 to create the PHY's TX_CORE_CLK.... 

I then looked at the JESD_PHY only example but they have not connected the PHY's TX_CORE_CLK or RX_CORE_CLK to logic, just a testbench.

 

You can seem I'm getting lost in clocks.... What is the right way to connect the PHY and Tx/Rx clocks togther please? :(

 

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cbemlahe
Explorer
Explorer
644 Views
Registered: ‎09-18-2007

OK, User Guide 576, Figure 3-4 gives an example on how to set up the clocks. I created a standalone Tx only example and there is a Verilog file "jesd204_0_clocking" which has the BUFG_GT, BUFG_GT_SYNC and IBUFDS_GTE3 primitives. I copied this and I now get through place and route and bitstream generation.

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cbemlahe
Explorer
Explorer
645 Views
Registered: ‎09-18-2007

OK, User Guide 576, Figure 3-4 gives an example on how to set up the clocks. I created a standalone Tx only example and there is a Verilog file "jesd204_0_clocking" which has the BUFG_GT, BUFG_GT_SYNC and IBUFDS_GTE3 primitives. I copied this and I now get through place and route and bitstream generation.

View solution in original post