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Newbie nick.sutch
Newbie
127 Views
Registered: ‎02-01-2019

Ultrascale AMI TX Pacakge issue

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I'm using Xilinx_UltraScale_GTH_AMI_Kit_Ver3p1p1, simulating a transmitter with xilinx_ultrascale_gth_ami_tx.ibs -> xilinx_ultrascale_gth_ami_tx_typical.s4p - > Xilinx_ultrascale_gth_Tx_Package.s4p -> PCB Channel -> Receiver. Simulated using HyperLynx LineSim VX2.4.

GTH_AMI_Setup.jpg

I observed some strange results in the eye diagram, it was basically a flat line with a couple of small peaks. I narrowed the issue down to the Xilinx_ultrascale_gth_Tx_Package.s4p (removing it gives me a sensible eye diagram). On closer inspection, it looks like the S(2,1) is attenuating the DC by -88dB. In fact, S(2,1) looks the same as S(1,1) and S(2,2) which is not what I would normally expect. I've attached a pdf of the response I am seeing.

Am I simulating this in the wrong way or is this an error in the s-parameters? 

Thanks,

Nick

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1 Solution

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Xilinx Employee
Xilinx Employee
102 Views
Registered: ‎10-19-2011

Re: Ultrascale AMI TX Pacakge issue

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Hi @nick.sutch,

can you check the port order of the placed models?
Please compare with user guide that comes with the model.

Can you adjust and try again?

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Xilinx Employee
Xilinx Employee
103 Views
Registered: ‎10-19-2011

Re: Ultrascale AMI TX Pacakge issue

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Hi @nick.sutch,

can you check the port order of the placed models?
Please compare with user guide that comes with the model.

Can you adjust and try again?

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
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Newbie nick.sutch
Newbie
52 Views
Registered: ‎02-01-2019

Re: Ultrascale AMI TX Pacakge issue

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Hi eschidl,

Thanks for your response. On closer inspection, I can see I got the ports wrong on the package model (I had connected them in the same away as the termination model). I have re-run the sim and all looks good.

 

Thanks,

NIck

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