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Registered: ‎09-28-2018

Ultrascale+ how to connect two different transceiver of same quad with two different reference clock

Hi,

I am trying to connect the two different clock one with 125MHz and other with 148.5MHz for the SFP+ and the SDI respectively.

I am not able to do that , as it is connecting clock to the QPLL0 , and all the transceiver will be connected to the either clock_0 or clock_1 of that GTH bank or corresponding bank 

 

So is there any alternative ?

 

Can I make changes to this while generating the example design for it?

 

Is there any method to enable the OPLL1 and also QPLL0 at the same time so i can connect the two different clock while generation of the example design or by the verilog code ?

 

Thanks 

Akshay 

AKSHAY
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

hi akshay.bhat@iwavesystems

 

 

So is there any alternative ? 

Can I make changes to this while generating the example design for it?

- example design may need some manual edit to suppor that.

 

Is there any method to enable the OPLL1 and also QPLL0 at the same time so i can connect the two different clock while generation of the example design or by the verilog code ?

GT Wizard GUI cannot fully support that, but you can follow below example as start point.

 

https://www.xilinx.com/support/answers/65228.html

 

Thanks,

Boris

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