VCU128 Board, Vivado 2019.1
I'm using two quads: X0Y3 and X0Y1. The two transceiver RX busses are split between the two quads as follows (snapshots below):
- transB = X0Y12 & X0Y7 & X0Y6 & X0Y4; (1 from X0Y3 and 3 from X0Y1)
- transC = X0Y15 & X0Y15 & X0Y13 & X0Y5; (3 from X0Y3 and 1 from X0Y1)
They share the same mgtrefclk, which is MGTREFCLK0 of X0Y3. I followed the guidelines shown in Figure 3-10 of PG182 as follows:
- transC has a COMMON block. transB does not.
- The outputs qpll0outclk_out, and qpll0outref_clk from transC are tied to inputs on transB qpll0clk_in and qpll0refclk_in.
I get an unroutable placement error (below). It says I have the option of overriding, so I'd like to know if that's a reasonable thing to do given my design.
Thanks very much for any help.
transB and transC:
ERROR:
[Place 30-738] Unroutable Placement! A GTYE_COMMON / GTYE_CHANNEL clock component pair is not placed in a routable site pair. The GTYE_COMMON component can use the dedicated path between the GTYE_COMMON and the GTYE_CHANNEL if both are placed in the same clock region.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[3].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/qpll0outclk_out[0]] >
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[3].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST (GTYE4_COMMON.QPLL0OUTCLK) is provisionally placed by clockplacer on GTYE4_COMMON_X0Y3 (in SLR 0)
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL0CLK) is locked to GTYE4_CHANNEL_X0Y12 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL0CLK) is locked to GTYE4_CHANNEL_X0Y13 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL0CLK) is locked to GTYE4_CHANNEL_X0Y14 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL0CLK) is locked to GTYE4_CHANNEL_X0Y15 (in SLR 0)
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL0CLK) is locked to GTYE4_CHANNEL_X0Y6 (in SLR 0)
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL0CLK) is locked to GTYE4_CHANNEL_X0Y7 (in SLR 0)
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y26 (in SLR 0)
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y26 (in SLR 0)
Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.RXOUTCLK) is locked to GTYE4_CHANNEL_X0Y7 (in SLR 0)
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X0Y26 (in SLR 0)
Clock Rule: rule_gtychannel_bufgsync_rx
Status: PASS
Rule Description: A GTYChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.RXOUTCLK) is locked to GTYE4_CHANNEL_X0Y7 (in SLR 0)
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y26 (in SLR 0)
Clock Rule: rule_bufggt_pll
Status: PASS
Rule Description: A BUFG_GT driving PLL must be in the same clock region row
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (BUFG_GT.O) is provisionally placed by clockplacer on BUFG_GT_X0Y26 (in SLR 0)
Clock Rule: rule_gtycommon_gtychannel
Status: PASS
Rule Description: A GTYCommon driving a GTYChannel must both be in the same clock region
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[3].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST (GTYE4_COMMON.QPLL1OUTCLK) is provisionally placed by clockplacer on GTYE4_COMMON_X0Y3 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL1CLK) is locked to GTYE4_CHANNEL_X0Y13 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL1CLK) is locked to GTYE4_CHANNEL_X0Y14 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL1CLK) is locked to GTYE4_CHANNEL_X0Y15 (in SLR 0)
Clock Rule: rule_bufds_gtycommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTYCommon must both be placed in the same or adjacent two clock
regions (top/bottom)
ibuf_mgtclkc (IBUFDS_GTE4.O) is locked to GTYE4_COMMON_X0Y3 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[1].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST (GTYE4_COMMON.GTREFCLK00) is provisionally placed by clockplacer on GTYE4_COMMON_X0Y1 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[3].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST (GTYE4_COMMON.GTREFCLK00) is provisionally placed by clockplacer on GTYE4_COMMON_X0Y3 (in SLR 0)
Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.RXOUTCLK) is locked to GTYE4_CHANNEL_X0Y13 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X0Y77 (in SLR 0)
Clock Rule: rule_gtychannel_bufgsync_rx
Status: PASS
Rule Description: A GTYChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.RXOUTCLK) is locked to GTYE4_CHANNEL_X0Y13 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y49 (in SLR 0)
Clock Rule: rule_gtycommon_gtychannel
Status: PASS
Rule Description: A GTYCommon driving a GTYChannel must both be in the same clock region
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_common.gen_common_container[1].gen_enabled_common.gtye4_common_wrapper_inst/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST (GTYE4_COMMON.QPLL0OUTCLK) is provisionally placed by clockplacer on GTYE4_COMMON_X0Y1 (in SLR 0)
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL0CLK) is locked to GTYE4_CHANNEL_X0Y5 (in SLR 0)
adc_transB/inst/gen_gtwizard_gtye4_top.adc_gty_B_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.QPLL0CLK) is locked to GTYE4_CHANNEL_X0Y4 (in SLR 0)
Clock Rule: rule_bufggt_pll
Status: PASS
Rule Description: A BUFG_GT driving PLL must be in the same clock region row
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (BUFG_GT.O) is provisionally placed by clockplacer on BUFG_GT_X0Y77 (in SLR 0)
Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y49 (in SLR 0)
and adc_transC/inst/gen_gtwizard_gtye4_top.adc_gty_C_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y77 (in SLR 0)
